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MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
SXGA Flat Panel Controller
FEATURES General
* * * * * *
Auto configuration of sampling clock frequency, phase, H/V center, as well as white balance. Auto detection of present or non-present or over range sync signals and their polarities. Composite sync separation and odd/even field detection of interlaced video. On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle and delay). Selection of serial 2-wire I2C or 8-bit direct host interface to 8-bit MCU. 3.3V supplier, 5V I/O tolerance in 256-pin PQFP or 272-pin BGA package. Single RGB (24-bit) or Dual RGB (48-bit) input rates up to 160MHz. Support both non-interlaced and interlaced RGB graphic input signals. YUV 4:2:2 or YUV 4:1:1 (CCIR601) interlaced video input. Glue-less connection to Philips SAA711x digital video decoder. Built-in YUV to RGB color space converter. Compliant with digital LVDS/PanelLink TMDS input interface. PC input resolution up to SXGA 1280x1024 @85Hz. Independent programmable Horizontal and Vertical scaling ratios from 1/32 to 32 Flexible de-interlacing unit for digital YUV video input data. Zoom to full screen resolution of de-interlaced YUV video data stream. Built-in programmable gain control for white balance alignments. Built-in programmable 8-bit or 10-bit gamma correction table. Built-in programmable temporal color dithering. Built-in programmable interpolation look-up table. Support smooth panning under viewing window change. Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output. Built-in output timing generator with programmable clock and H/V sync. Support VGA/SVGA/XGA/SXGA display resolution. Overlay input interface with external OSD controller. Double scan capability for interlaced input. Support 48/32/24 bit bus width, SDRAM/SGRAM x2 or x3 configuration. Optional display through internal line buffer without external frame-buffer memory. Support power down mode.
Input Processor
* * * * * * *
Video Processor
* * * * * * * *
Output Processor
* * * * *
Memory Interface
* * *
GENERAL DESCRIPTION
The MTL003 Flat Panel Display (FPD) Controller is an input format converter for TFT-LCD Monitor or LCD TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV signals from digital video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It includes a RGB/YUV input processor, configurable frame-buffer memory interface, video scaling up/down processor, OSD input interface and output display processor in 256-pin PQFP or 272-pin BGA package.
Revision 0.95
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2000/06/14
MYSON TECHNOLOGY
BLOCK DIAGRAM
MTL003
(Rev. 0.95)
To SDRAM/SGRAM
To external OSD
Digital video
YUV Input
YUV to RGB Scale Down Frame Buffer Control Scale Up Dithering
PC RGB
RGB Input
OSD & Output MUX
RGB output
Gain Control Auto Calibration Mode Detect Host Interface
Gamma Correct
Output & Memory Timing Generator
To 8-bit MCU
APPLICATIONS
LVDS/PanelLink TMDS Receiver Composite/ S-Video
SDRAM/ SGRAM
MTV130 OSD
Digital Video Decoder ADC1 ADC2
MTL003 FPD Monitor Controller
D-sub RGB graphic signals
TFT-LCD Flat Panel
MTV212 8-bit MCU
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 0.95
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MYSON TECHNOLOGY
1. PIN CONNECTION
MTL003
(Rev. 0.95)
PVSS *193 PVSS *194 MWE# *195 MCAS# *196 MRAS# *197 DQM1 *198 DQM0 *199 DVSS *200 DVDD *201 MD7 *202 MD6 *203 MD5 *204 MD4 *205 MD3 *206 MD2 *207 MD1 *208 MD0 *209 PVDD *210 MD31 *211 MD30 *212 MD29 *213 MD28 *214 MD27 *215 MD26 *216 MD25 *217 MD24 *218 PVSS *219 AD0 *220 AD1 *221 AD2 *222 AD3 *223 AD4 *224 AD5 *225 AD6 *226 AD7 *227 HCS# *228 PVDD *229 ALE *230 PVSS *231 HWR# *232 HRD# *233 EXTMCLK *234 RST# *235 BUSSEL *236 IRQ *237 GPIO7 *238 GPIO6 *239 GPIO5 *240 GPIO4 *241 GPIO3 *242 GPIO2 *243 GPIO1 *244 GPIO0 *245 EXTDCLK *246 CLAMP *247 HSYNC/CS*248 VSYNC *249 TMDSSEL *250 TDIE/SOG*251 PVDD *252 IPCLK *253 NC *254 PVSS *255 PVSS *256
Note: Pin connection of 272-pin BGA to be defined later
Revision 0.95
PVDD PVSS OSDRED OSDGRN OSDBLU OSDEN OSDINT OVSYNC DVSS OHSYNC DVDD MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 DQM2/MA9 DQM3/MA10 DVSS MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 DVDD MD15 MD14 MD13 MD12 MD11 MD10 MD9 MD8 MCS# DVSS MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 MCKE DVDD MCK PVSS BA/MA11 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 PVDD *129 *130 *131 *132 *133 *134 *135 *136 *137 *138 *139 *140 *141 *142 *143 *144 *145 *146 *147 *148 *149 *150 *151 *152 *153 *154 *155 *156 *157 *158 *159 *160 *161 *162 *163 *164 *165 *166 *167 *168 *169 *170 *171 *172 *173 *174 *175 *176 *177 *178 *179 *180 *181 *182 *183 *184 *185 *186 *187 *188 *189 *190 *191 *192
MTL003
(256-pin PQFP)
128* 127* 126* 125* 124* 123* 122* 121* 120* 119* 118* 117* 116* 115* 114* 113* 112* 111* 110* 109* 108* 107* 106* 105* 104* 103* 102* 101* 100* 99* 98* 97* 96* 95* 94* 93* 92* 91* 90* 89* 88* 87* 86* 85* 84* 83* 82* 81* 80* 79* 78* 77* 76* 75* 74* 73* 72* 71* 70* 69* 68* 67* 66* 65*
PVSS PVSS OCLK PVDD DDEN DVSYNC DHSYNC DVDD R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 R1OUT5 R1OUT6 R1OUT7 DVSS G1OUT0 G1OUT1 G1OUT2 G1OUT3 G1OUT4 G1OUT5 G1OUT6 G1OUT7 B1OUT0 B1OUT1 B1OUT2 B1OUT3 B1OUT4 B1OUT5 B1OUT6 B1OUT7 DVSS DDCLK1 DDCLK2 DVDD R2OUT0 R2OUT1 R2OUT2 R2OUT3 R2OUT4 R2OUT5 R2OUT6 R2OUT7 PVDD G2OUT0 G2OUT1 G2OUT2 G2OUT3 G2OUT4 G2OUT5 G2OUT6 G2OUT7 B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 B2OUT5 B2OUT6 B2OUT7 PVSS PVSS
64* 63* 62* 61* 60* 59* 58* 57* 56* 55* 54* 53* 52* 51* 50* 49* 48* 47* 46* 45* 44* 43* 42* 41* 40* 39* 38* 37* 36* 35* 34* 33* 32* 31* 30* 29* 28* 27* 26* 25* 24* 23* 22* 21* 20* 19* 18* 17* 16* 15* 14* 13* 12* 11* 10* 9* 8* 7* 6* 5* 4* 3* 2* 1* PVDD AVDD AVDD XI XO AVSS AVSS PVSS B2IN0 B2IN1 B2IN2 B2IN3 B2IN4 B2IN5 B2IN6 B2IN7 PVDD G2IN0 G2IN1 G2IN2 G2IN3 G2IN4 G2IN5 G2IN6 G2IN7 PVSS R2IN0 R2IN1 R2IN2 R2IN3 R2IN4 R2IN5 R2IN6 R2IN7 DVDD RGBSEL DVSS B1IN0 B1IN1 B1IN2 B1IN3 B1IN4 B1IN5 B1IN6 B1IN7 DVDD G1IN0/UVIN0 G1IN1/UVIN1 G1IN2/UVIN2 G1IN3/UVUN3 G1IN4/UVIN3 G1IN5/UVUN5 G1IN6/UVUN6 G1IN7/UVIN7 DVSS R1IN0/YIN0 R1IN1/YIN1 R1IN2/YIN2 R1IN3/YIN3 R1IN4/YIN4 R1IN5/YIN5 R1IN6/YIN6 R1IN7/YIN7 PVDD
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2. PIN DESCRIPTION ADC1 Input Interface (YUV or RGB or TMDS Input Data)
Name VSYNC HSYNC/CS RGBSEL TMDSSEL CLAMP IPCLK R1IN[7:0]/YIN[7:0] G1IN[7:0]/UVIN[7:0] B1IN[7:0] TDIE Type I I O O O I I I I I Pin# 249 248 29 250 247 253 2-9 11-18 20-27 251
MTL003
(Rev. 0.95)
Description Vertical sync input Horizontal or Composite sync input Input select. 1:RGB input, 0:YUV input TMDS input select, active high Clamp pulse output for ADC Input pixel clock Red or Y channel or TMDS input data (Single/Dual ADC) Green or UV channel or TMDS input data (Single/Dual ADC) Blue channel or TMDS input data (Single/Dual ADC) TMDS digital input enable
ADC2 Input Interface (RGB Data)
Name R2IN[7:0] Type I Pin# 31-38 Description Red channel input data (Dual ADC) or Control bit for YUV video input Bit 4: VPHREF, Video input Horizontal reference signal Bit 3: VPVS, Video input VSYNC signal Bit 2: VPODD, Video input ODD/EVEN field signal Bit 1: VPHS, Video input HSYNC signal Bit 0: VPCLK, Video input clock signal Green channel input data (Dual ADC) Blue channel input data (Dual ADC)
G2IN[7:0] B2IN[7:0]
I I
40-47 49-56
Display Output Interface
Name DDEN DVSYNC DHSYNC DDCLK1 DDCLK2 R1OUT[7:0] G1OUT[7:0] B1OUT[7:0] R2OUT[7:0] G2OUT[7:0] B2OUT[7:0] Type O O O O O O O O O O O Pin# 124 123 122 94 93 113-120 104-111 96-103 84-91 75-82 67-74 Description Display data output enable for LCD panel Display Vertical sync output Display Horizontal sync output Display output clock for odd data Display output clock for even data Red output even data , bit[7:2] for 6-bit panel Green output even data , bit[7:2] for 6-bit panel Blue output even data , bit[7:2] for 6-bit panel Red output odd data , bit[7:2] for 6-bit panel Green output odd data , bit[7:2] for 6-bit panel Blue output odd data , bit[7:2] for 6-bit panel
Memory Interface
Name MCK MCKE MCS# MRAS# MCAS# MWE# DQM[1:0] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] Revision 0.95 Type O O O O O O O O O O O Pin# 180 178 168 197 196 195 198-199 182 149 148 183-191 Description Memory output clock Memory clock enable Memory chip select, active low. Memory row address strobe, active low Memory column address strobe, active low Memory write enable, active low Memory data mask byte enable Memory bank address or Memory address line SGRAM data mask byte enable or SDRAM address line SGRAM data mask byte enable or SDRAM address line Memory address line -42000/06/14
MYSON TECHNOLOGY
MD[47:40] MD[39:32] MD[31:24] MD[23:16] MD[15:8] MD[7:0] I/O I/O I/O I/O I/O I/O 151-158 170-177 211-218 140-147 160-167 202-209 Memory Blue (B1) data Memory Green (G1) data Memory Red (R1) data Memory Blue (B0) data Memory Green (G0) data Memory Red (R0) data
MTL003
(Rev. 0.95)
Host Interface
Name RST# AD[7:0] Type I I/O Pin# 235 227-220 Description System reset input, active low. The address and data bus of 8-bit direct interface or 2-wire I2C series bus Bit 1: SDA, serial bus data Bit 0: SCK, serial bus clock Host write strobe, active low Host read strobe, active low Host address latch enable for 8-bit direct bus Host chip select Bus mode selection. 0: I2C bus, 1: 8-bit direct bus Interrupt request output
HWR# HRD# ALE HCS# BUSSEL IRQ
I I I I I O
232 233 230 228 236 237
OSD Interface
Name OCLK OVSYNC OHSYNC OSDRED OSDGRN OSDBLU OSDINT OSDEN Type O O O I I I I I Pin# 126 136 138 131 132 133 135 134 Description Clock for external OSD Vertical sync for external OSD Horizontal sync for external OSD OSD red input OSD green input OSD blue input OSD intensity input OSD overlay enable
Other Interface
Name XI XO EXTDCLK EXTMCLK GPIO[7:0] Type I O I I I/O Pin# 61 60 246 234 238-245 Description Oscillator frequency input Oscillator frequency output External display clock input External memory clock input General purpose I/O or Bit 7: ADVS, Vertical sync for A/D converter Bit 6: ADHS, Horizontal sync for A/D converter Bit 2: MA9_SGRAM, Memory address 9 for SGRAM Bit 0: RAWHS/SOG, Input source HSYNC or Input Sync On Green Default: Bit[7:2]: Output direction Bit[1:0]: Input direction No connection
NC
-
254
3.3V Power and Ground
Name DVDD DVSS PVDD PVSS Revision 0.95 Pin# 19, 30, 92, 121, 139, 159, 179, 201 10, 28, 95, 112, 137, 150, 169, 200 1, 48, 64, 83, 125, 129, 192, 210, 229, 252 39, 57, 65, 66, 127, 128, 130, 181, 193, 194, -5Description Digital power 3.3V Digital ground Pad power 3.3V Pad ground 2000/06/14
MYSON TECHNOLOGY
AVDD AVSS 219, 231, 255, 256 62, 63 58, 59
MTL003
(Rev. 0.95)
Analog power 3.3V Analog ground
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3. FUNCTIONAL DESCRIPTION 3.1 Input Processor
MTL003
(Rev. 0.95)
General Description The function of Input Interface is to provide the interface between MTL003 and external input devices. It can process both non-interlaced and interlaced RGB graphic input, YUV video input, and digital RGB input compliant with digital LVDS/PanelLink TMDS interface. It also contains the Decimation circuit to scale down the input image with arbitrary ratios down to 1/32 and the built-in YUV to RGB color space converter. 3.1.1 RGB Input Format The RGB input port can work in two modes: Single Pixel mode (24 bits) and Double Pixel mode (48 bits). For Single Pixel mode, only the ports R1IN[7:0], G1IN[7:0], and B1IN[7:0] are internally sampled. For Double Pixel mode, besides the ports R1IN[7:0], G1IN[7:0], and B1IN[7:0], the ports R2IN[7:0], G2IN[7:0], and B2IN[7:0] are needed additionally. The R/G/B1IN ports are sampled at the rising edge of the RGB input clock, and the R/G/B2IN ports are sampled at the falling edge. 3.1.2 TMDS Input Format The Digital RGB input port works just in the same way as Sec 3.1.1 except that pin "Digital Input Enable DIEN" is needed. With a flexible single or double pixel input interface, the supported format is up to true color, including the 18 bit/pixel or 24 bit/pixel in 1 or 2 pixels/clock mode. 3.1.3 YUV Input Format The YUV input port supports interlaced video data from the most common video decoder ICs like SAA711x. The 16 bit data bus is shared with the ports R1IN[7:0] and G1IN[7:0]. The 5 bit control signals are shared with the port R2IN[4:0]. The 16 bit data is sampled at the rising edge of the shared video clock VPCLK when the shared data enable HREF is active. The supported formats are YUV4:1:1 and YUV4:2:2 with CCIR601 standard. 3.1.4 YUV to RGB Converter Is used to convert YCbCr format into RGB format. The basic equations are as follows: R = Y + 1.371(Cr - 128) G = Y - 0.698(Cr - 128) - 0.336(Cb - 128) B = Y + 1.732(Cb - 128) 3.1.5 De-interlace mode For interlace input, MTL003 features several de-interlacing algorithms for processing interlaced video data depending on the type of input images.
Static Mode In this mode, the first and second fields are put together without any filtering. Memory for two fields is needed. It is commonly used in still image input.
Toggle Mode In this mode, only one field is displayed at a time. First field and second field is toggled displayed. The missing lines are calculated from duplicating the neighboring lines. For moving picture, it has a good quality.
Spatial Mode In this mode, two fields are toggled displayed, just like Toggle mode. The missing lines are calculated from interpolating the neighboring lines. This mode has an generally good quality for still and moving pictures. 3.1.6 Sync Processor The V/H SYNC processing block performs the functions of Composite signal separation/insertion, SYNC inputs the presence check, frequency counting, polarity detection and control. It contains a de-glitch circuit to filter out any pulse shorter than one OSC period which is treated as noise among V/H SYNC pulses. Revision 0.95 -72000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
V/H SYNC Frequency Counter MTL003 measures VSYNC/HSYNC frequency counted in the proper clock and using the following formulae: fvsync = fosc / Nvsync 51/256 fhsync = fosc / Nhsync 58 Where fvsync fhsync fosc Nvsync Nhsync : VSYNC frequency : HSYNC frequency : oscillator clock with 14.31818 MHz : counted number of VSYNC : counted number of HSYNC
V/H SYNC Presence Check This function checks the input VSYNC, where Vpre flag is set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz and the input is HSYNC, where Hpre flag is set when HSYNC is over 10KHz or cleared when HSYNC is under 10Hz.
V/H Polarity Detect This function detects the input VSYNC/HSYNC high and low pulse duty cycle. If the high pulse duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted.
Composite SYNC separation/insertion MTL003 continuously monitors the input HSYNC. If the input VSYNC can be extracted from it, a CVpre flag is set. MTL003 can insert HSYNC pulse during Composite VSYNC' active time and the insertion frequency s can adapt to original HSYNC' s. 3.1.7 Auto Tune Auto Tune function consists of Auto Position that automatically centering the screen and Auto Calibration which contains Phase Calibration, Histogram, Min/Max Value, and Pixel Grab described as below. With this auto adjustment support it is possible to measure the correct phase, frequency, gain, and offset of ADC. The horizontal and vertical back porches of input image and the horizontal and vertical active regions can also be measured. Firmware can adjust input image registers automatically by reading Auto Tune' registers in single s or burst mode.
Auto Position MTL003 provides Horizontal/Vertical back porch and active region values. Users can use these values to set input sample registers to aid in centering the screen automatically.
Phase Calibration MTL003 provides Auto Calibration registers to measure the quality of current ADC' phase and frequency. s The biggest Auto Calibration registers value means the right value of ADC' phase and frequency. MTL003 s has two kinds of algorithms to calculate Auto Calibration' value. One is the traditional Difference method, the s other is MYSON' proprietary method; the latter one is recommended for a better performance. s
Histogram Histogram means the total number of input pixels below/above one threshold value, for individual R/G/B colors. This advanced function helps the firmware to analyze ADC performance. Usually the firmware can use this information to measure ADC' noise margin, and adjust its offset and gain, or even aid in the mode s detection.
Min/Max Value Min/Max value means minimum or maximum pixel value within the specified input active image region for each RGB channel. This information is usually used to adjust ADC' offset and gain. s
Pixel Grab Pixel Grab means users can grab a single input pixel at any one point. The position of the point can be programmed by users. This is another traditional method to measure ADC' phase and frequency. s
Revision 0.95
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MYSON TECHNOLOGY
3.2 Video Processor
MTL003
(Rev. 0.95)
General Description MTL003 possesses a powerful and programmable video processor by providing the following functions: Scaling Up/Down, Gain Control, Brightness Control, Gamma Correction, and Dithering Control. The block diagram of Video Processor is as follows:
Scaling Factor SCALING Transition Table
GAIN
Gain Factor
BRIGHTNESS
Brightness Factor
GAMMA
Gamma Table
DITHERING
Dithering Table
Fig. 3.2.1 Video Processor Block Diagram
3.2.1 Scaling MTL003 provides scaling function ranging from 1/32 to 32 for both up and down scaling, and for both horizontal and vertical processing. Note that the up and down scaling cannot operate in the same time, because they share the same line buffers. For scaling up, both horizontal and vertical processing, MTL003 provides four methods:

Pass Mode: Image will be passed through without considering any scaling factor. Duplicate Mode: Image will be scaled up/down based on scaling factor. Every point of output image comes from the input. In this method, Output image will have the good contrast but may be nonuniformed. Bilinear Mode: Image will be scaled up/down based on scaling factor. Every point of output image data will be filtered by bilinear filter. In this method, output image will have the good scaling quality but may be blurred. Interpolation Table Mode: Image will be scaled up/down based on scaling factor. Every point of output image data will be filtered by the user defined filter.
Revision 0.95
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MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
Input pixel
A
B
Interpolation pixel SC 64 SC'
O
[a] 63 [a]: duplicate filter [b]: bilinear filter 32 [b] [c] [c]: user defined filter O = [(64-SC' + SC' )*A *B]/64 SC 32 Fig. 3.2.2 Scaling filter 63
Note: For scaling down, for both horizontal and vertical processing, MTL003 provides three methods: Pass mode, Duplicate mode, and Bilinear mode. 3.2.2 Gain/Brightness Control MTL003 provides Gain and Brightness control to adjust the contrast and brightness of output color by programming the gain and brightness coefficients. This adjustment is applied to RGB colors individually. Auto-white balance can be achieved by using this function. 3.2.3 Gamma Correction Gamma Correction is used to compensate the non-linearity of LCD display panel. MTL003 contains an 8/10bit Gamma table to fix this phenomenon. The 10-bit Gamma Table performs a better output quality, and is commonly used together with dithering function. A traditional 8-bit Gamma correction table can also be used. 3.2.4 Color Dithering MTL003 supports true color (8 bits per color) or high color (6 bits per color) display. In the latter case, users can turn on dithering function to avoid artificial contour due to truncation. The dithering function works in two modes:

Static dithering: Dithering coefficient is fixed. Temporal dithering: Dithering coefficient is time dependent.
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MYSON TECHNOLOGY
3.3 Output Processor
MTL003
(Rev. 0.95)
General Description Output processor provides the interface for both LCD panel and OSD controller. MTL003 can work for framebuffer or non-frame-buffer mode. When in frame-buffer mode, there is no restriction between the timing of input and output. When in non-frame-butter mode, output frame rate must be equal to input frame rate and output display time must be equal to input display time due to the absence of frame buffer. Some features based on using the frame buffer do not work in non-frame-buffer mode, for example the screen write, static mode in de-interlace etc. 3.3.1 Display Timing Generation There are three display timing modes:

Frame-buffer Mode: is used for frame rate conversion. External frame buffer is needed. Non-frame-buffer Mode: performs a low cost version of solution where the external frame buffer is not needed. This mode is used in the condition that output frame rate is equal to input frame; some features are disabled in this mode. Frame SYNC Mode: is used for video input. In this mode, output frame is synchronized to input frame, gives the moving picture a smooth change. Frame Buffer Mode: Input Frame Output Frame
External Frame Buffer Non Frame Buffer Mode Input Frame x Lock point
Output Frame
Frame SYNC Mode Input Frame x Lock point
Output Frame
External Frame Buffer Fig. 3.2.3 Display Timing modes
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MTL003
(Rev. 0.95)
3.3.2 OSD Overlay MTL003 allows the integration of overlay data with the scaled output pixel stream. It provides a fully compatible OSD interface. Individual OSD clock, OSD HSYNC and OSD VSYNC are sent to external OSD device. MTL003 receives OSD Enable, OSD Red, OSD Green, OSD Blue, and OSD Intensity from external OSD device. 3.3.3 RGB Output Format MTL003 output interface consists of two pixel ports, each containing Red, Green, and Blue color information with a resolution of 6/8 bits per color. These two ports are PORT1 and PORT2 respectively. The control signals for output port are the display horizontal sync signal (DHSYNC), the display vertical sync signal (DVSYNC) and the display data enable signal (DDEN). All the signals mentioned above are synchronous to the output clock. The output timing relative to the active edge of the output clock is programmable. There are two RGB output formats:
Single Pixel Mode Is designed to support TFT panels with single pixel input. Only PORT1 is active. The frequency of DCLK1 is equal to the internal display clock.
Dual Pixel Mode Is designed to support TFT panels with dual pixel input. PORT1 and PORT2 are used. The first pixel is at PORT1, and the second at PORT2.
DCLK DDEN
SINGLE PORT DUAL PORT
Revision 0.95
R1OUT/G1OUT /B1OUT DCLK DCLK1 DCLK2 DDEN R1OUT/G1OUT /B1OUT R2OUT/G2OUT /B2OUT
000
rgb0 rgb1 rgb2 rgb3
rgb4
000 000
rgb0 rgb2 rgb4 rgb6 rgb1 rgb3 rgb5 rgb7
rgb8 rgb9
Fig. 3.2.4 Display Data Timing
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3.4 Memory Interface
MTL003
(Rev. 0.95)
General Description In frame buffer mode, the MTL003 connects to the external frame buffers by means of memory interface. The external frame memory can be made for 1M516bits SDRAM, 256K532bits or 512K532bits SGRAM devices. Due to different applications such as VGA, SVGA, XGA as well as SXGA, the image resolution of input and output will be limited resulting from the bandwidth of memory interface. Two configurations with 24, 32 and 48 bits bus modes will be supported to resolve the bandwidth constraint in most of applications. The clock for external frame memory devices can be provided from the internal PLL circuit or the external clock applied to pin EXTMCLK and its frequency can be up to 118 MHz. The MTL003 also supplies a simple and complete memory self-testing mechanism for SDRAM and SGRAM, which can be used to detect memory cell status and to check connection in memory interface. 3.4.1 SDRAM Configuration In current applications, the most popular organization of SDRAM is 1M516bits. To achieve the desired bandwidth in memory interface, 2 or 3 devices have to be constructed in parallel. The memory clock range is from 50Mhz to 118Mhz by tuning the appropriate parameters for the internal PLL circuit. In two devices configuration, the 24 and 32 bits bus modes are supported. By these modes, the maximum input image resolution can be supported up to 10245768 @ 60Hz and 10245768 @ 85Hz respectively. The 48 bits bus mode in 3 devices will provide the maximum input image resolution up to 128051024 @ 75Hz. Table 3.4.1 gives the configuration for different input and output image format. Figure 3.4.1 shows the connection between the MTL003 and SDRAM devices in 2 configurations. Unit: device Output Resolution SVGA XGA SXGA Input Resolution YUV 2 2 2 VGA (6405480) 2 2 2 SVGA (8005600) 2 2 2 XGA (10245768) 2 2 2 SXGA (128051024) 3 3 3 Table 3.4.1 SDRAM configuration in different input and output modes 3.4.2 SGRAM Configuration The SGRAM devices in 256K532bits and 512K532bits constructions are usually used to feature the wide data bus for high speed applications. In case of SGRAM usage, the 32 bits data bus of each device is divided into 2 parts to store input image data. The memory clock is able to be set the desired range as SDRAM case as well. In two devices(512K532bits) configuration, the 24 and 32 bits bus modes are supported. By these modes, the maximum input image resolution can be supported up to 10245768 @ 60Hz and 10245768 @ 85Hz respectively. The 48 bits bus mode in 3 devices(512K532bits) will provide the maximum input image resolution up to 128051024 @ 75Hz. Table 3.4.2 provides the configuration for different input and output image format. Figure 3.4.2 and 3.4.3 show the connection between the MTL003 and SGRAM devices in 2 configurations by 256K532bits and 512K532bits constructions respectively.. Unit: device Output Resolution SVGA XGA SXGA Input Resolution YUV 2 2 2 VGA (6405480) 2 2 2 SVGA (8005600) 2 2 2 XGA (10245768) (512Kx32bits / 256Kx32bits) 2/3 2/3 2/3 SXGA (128051024) (512K532bits only) 3 3 3 Table 3.4.2 SGRAM configurations in different input and output modes
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SDRAM(1M516bits) 5 2
MD[7:0] MD[31:24] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] DQM0 DQM1 MCK MCKE MCS # RAS# M MCAS# MWE# DQ7~0 DQ15~8 BA A10 A9 A8~0 LDQM UDQM CLK CKE /CS /RAS /CAS /WE MD[15:8] MD[39:32] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] DQM0 DQM1 MCK MCKE MCS # RAS# M MCAS# MWE# DQ7~0 DQ15~8 BA A10 A9 A8~0 LDQM UDQM CLK CKE /CS /RAS /CAS /WE
MTL003
(Rev. 0.95)
SDRAM(1M516bits) 5 3
MD[7:0] MD[31:24] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] DQM0 DQM1 MCK MCKE MCS # MRAS# MCAS# MWE# DQ7~0 DQ15~8 BA A10 A9 A8~0 LDQM UDQM CLK CKE /CS /RAS /CAS /WE MD[15:8] MD[39:32] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] DQM0 DQM1 MCK MCKE MCS # MRAS# MCAS# MWE# DQ7~0 DQ15~8 BA A10 A9 A8~0 LDQM UDQM CLK CKE /CS /RAS /CAS /WE MD[23:16] MD[47:40] BA/MA11 DQM3/MA10 DQM2/MA9 MA[8:0] DQM0 DQM1 MCK MCKE MCS # MRAS# MCAS# MWE# DQ7~0 DQ15~8 BA A10 A9 A8~0 LDQM UDQM CLK CKE /CS /RAS /CAS /WE
Fig. 3.4.1 The interface between MTL003 and 1Mx16 bits SDRAM
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MYSON TECHNOLOGY
SGRAM(128K532bits52 ) 5 2
MD[7:0] MD[31:24] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 BA/MA11 MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE# 4 A9(BA) A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F BA/MA11 MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE# MD[15:8] MD[39:32] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A9(BA) A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F
MTL003
(Rev. 0.95)
SGRAM(128K532bits52 ) 5 3
MD[7:0] MD[31:24] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A9(BA) A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F MD[15:8] MD[39:32] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A9(BA) A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F MD[23:16] MD[47:40] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A9(BA) A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F
BA/MA11 MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE#
BA/MA11 MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE#
BA/MA11 MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE#
Fig. 3.4.2 The interface between MTL003 and 256Kx32 bits SGRAM
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MYSON TECHNOLOGY
SGRAM(256K532bits52 ) 5 2
MD[7:0] MD[31:24] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A10(BA) A9 A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F MD[15:8] MD[39:32] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 BA/MA11 GPIO[2] MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE# 4 A10(BA) A9 A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F
MTL003
(Rev. 0.95)
BA/MA11 GPIO[2] MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE#
SGRAM(256K532bits52 ) 5 3
MD[7:0] MD[31:24] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 BA/MA11 GPIO[2] MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE# 4 A10(BA) A9 A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F BA/MA11 GPIO[2] MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE# MD[15:8] MD[39:32] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A10(BA) A9 A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F MD[23:16] MD[47:40] DQ7~0 DQ15~8 DQ23~1 6 DQ31~2 4 A10(BA) A9 A8~0 DQM0 DQM1 DQM2 DQM3 CLK CKE /CS /RAS /CAS /WE DS F
BA/MA11 GPIO[2] MA[8:0] DQM0 DQM1 DQM2/MA9 DQM3/MA10 MCK MCKE MCS # MRAS# MCAS# MWE#
Fig. 3.4.3 The interface between MTL003and 512Kx32 bits SGRAM
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MYSON TECHNOLOGY
3.5 Host Interface
MTL003
(Rev. 0.95)
General Description The primary function of Host Interface is to provide the interface between MTL003 and external CPU by 2wire I2C Bus or Direct Bus selected by the input pin BUSSEL. It can generate all the I/O decoded control timing to control all the registers in MTL003. The other function is Screen Write, which allows users to clear frame buffer, and display output as well. 3.5.1 I2C Serial Bus The I2C serial interface use 2 wires, SCK (clock) and SDA(data I/O). The SCK is used as the sampling clock and SDA is a bi-directional signal for the data. The communication must be started with a valid START condition, concluded with STOP condition and acknowledged by ACK condition by the receiver. The I2C bus device address of MTL003 is 0111010x. AD[0] AD[1] SCK, serial bus clock. SDA, bi-directional serial bus data.
The START condition means a HIGH to LOW transition of SDA when SCK is high, the STOP condition means a LOW to HIGH transition of SDA when SCK is high. Data of SDA only changes when SCK is low. Ref. Fig.3.5.1. SDA
SCK
START
DATA CHANGE
DATA CHANGE
STOP
Fig. 3.5.1 START, STOP ,and DATA definition The I2C interface supports Random Write, Sequential Write, Current Address Read, Random Read and Sequential Read operations.
Random Write For Random Write operation, it contains the slave address with R/W bit set to 0 and the word address which is comprised of 8 bits that provides the access to any one of the 256 bytes in the selected memory range. Upon receipt of the word address, MTL003 responds with an Acknowledge and waits for the next eight bits of data again, responding with an Acknowledge, and then the master generates a stop condition. Ref. Fig.3.5.2.
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MYSON TECHNOLOGY
S T A R T SDA WA C K Fig. 3.5.2 Random Write
MTL003
(Rev. 0.95)
SLAVE ADDRESS
WORD ADDRESS
DATA
S T O P
A C K
A C K
Sequential Write The initial step of Sequential Write is the same as Random Write, after the receipt of each word data, MTL003 will respond with an Acknowledge and then internal address counter will increment by one for next data write. If the master stops writing data, it will generate stop condition. Ref. Fig. 3.5.3.
S T A R SLAVE T ADDRESS SDA WA C K
WORD ADDRESS
DATA n
DATA n+1
DATA n+x
S T O P
A C K
A C K
A C K
A C K
Fig. 3.5.3 Sequential Write
Current Address Read MTL003 contains an address counter which maintains the last access address incremented by one. If the last access address is n, the read data should access from address n+1. Upon receipt of the slave address with R/W bit set to 1, MTL003 generates an Acknowledge and transmits the eight bits data. After receiving data the master will generate a stop condition instead of an Acknowledge. Ref. Fig. 3.5.4.
S T A R T SDA
SLAVE ADDRESS
DATA
S T O P
RA C K Fig. 3.5.4 Current Address Read
Revision 0.95
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MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
Random Read The operation of Random Read allows access to any address. Before the reading data operation, it must issue a "dummy write" operation -- the master issues the start condition, slave address and then the word address it is to read. After the word address acknowledge, the master generating a start condition again and slave address with R/W bit is set to 1. MTL003 then transmits the 8 bits of data. Upon the completion of receiving data, the master will generate a stop condition instead of an Acknowledge. Ref. Fig 3.5.5.
S T A R T SDA
SLAVE ADDRESS
WORD ADDRESS
S T A R T A C K
SLAVE ADDRESS
DATA
S T O P
WA C K
RA C K
Fig. 3.5.5 Random Read
Sequential Read The initial step can be as either Current Address Read or Random Read. The first read data is transmitted in the same manner as other read methods. However, the master generates an Acknowledge indicating that it requires more data to read. MTL003 continues to output data for each Acknowledge received. The output data is sequential and the internal address counter increments by one for next read data. Ref. Fig. 3.5.6. S T A R T SDA RA C K A C K A C K
SLAVE ADDRESS
DATA n
DATA n+1
DATA n+x
S T O P
Fig. 3.5.6 Sequential Read 3.5.2 8-bit Direct Bus The Direct Bus use AD[7:0], HWR#, HRD#, ALE, HCS# as the interface with host. ALE is used to latch read or write address from AD[7:0] and HRD#, HWR# to access data. Ref. Fig. 3.5.7. AD[7:0] HRD# HWR# ALE HCS# Address and data multiplex bus. CPU read data strobe, Active Low. CPU write data strobe, Active Low. ALE =1 latch read or write address, ALE=0 represents I/O data. Enable signal for CPU access, Active Low.
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AD[7:0] ADDRESS DATA
MTL003
(Rev. 0.95)
ALE
HWR/HRD Fig. 3.5.7 Direct Bus Timing 3.5.3 Interrupt MTL003 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to firstly check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide what events are happening. After the operation is completed, Firmware needs to clear interrupt status by writing the same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg. EAh and EBh), each interrupt event can be masked. 3.5.4 Screen Write Screen Write function can be used to clear frame buffer memory and display output by a fixed value defined in Reg. C6h, C7h, C8h. 3.5.5 Bi-directional GPIO MTL003 supports eight General Purpose Input and Output (GPIO) pins GPIO[7:0] on chip. The GPIO[5:0] pins are bi-directional GPIO pins, and the GPIO[7:6] pins are output only GPIO pins. There are two functions for GPIO[7:6] pins. One is to set them as output only GPIO pins, and the other is to set them as Composite decoded VSYNC/HSYNC for A/D converters in VGA input path. The data and I/O direction of GPIO[7:0] pins are controlled by Reg. F4h and F5h respectively, and each bit in the register is mapped to GPIO[7:0] correspondingly. The following description is the process to control GPIO[0] and GPIO[6] in detail, and the control processes of GPIO[4:1] and GPIO[7] also follows in the same manner.
Bi-directional GPIO control process q Setting Reg. F5h/D0 = 0 or 1 to assign GPIO[0] as output or input. q Writing data to Reg. F4h/D0 when GPIO[0] is assigned to output status, otherwise reading data from Reg. F4h/D0 when GPIO[0] is input. Output only GPIO control process q Setting Reg. F5h/D6 = 0 or 1 to assign GPIO[6] as output or tri-state. q Setting Reg. F6h/D0 = 0 to select output source from Reg. F4h/D6 or setting it as 1 to make GPIO[6] pin to output ADHS which is HSYNC signal decoded from VGA input Composite signal by the MTL003. q Writing data to F4h/D6 when GPIO[6] is assigned to output only GPIO pin, that is, F6h/D0 = 0 and F5h/D6 = 0. If F6h/D0 is set to 1, the GPIO[6] pin outputs ADHS for AD converters in VGA input path.
3.5.6 Update Register Contents I/O write operation to some consecutive register set can have the "Double Buffer" effect by setting the Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transferred to the active register set by setting Reg. C1h/D1-0.
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MYSON TECHNOLOGY
3.6 On-Chip PLL
MTL003
(Rev. 0.95)
General Description The MTL003 needs three clock sources to drive synchronous circuits on chip. These clocks are generated from the internal Phase Lock Loop (PLL) circuits with reference to the oscillator clock which is applied to pin XI and XO by an external quartz crystal at 14.31818 MHz. The first one is the same as to the oscillator clock at frequency (14.31818 MHz) to detect and measure graphic vertical and horizontal SYNC Frequency, Polarity as well as Presence. The second is memory clock to synchronize memory controller with the external frame buffers. The third is the display clock for display controller on chip and output signals to LCD panel. 3.6.1 Reference Clock It is the counting basis of counter values in SYNC Processor such as VS and HS period count registers; that is, the read back values from these registers must multiply the period of this clock to estimate VS and HS frequency. Incorporating with polarity and frequency information of VS and HS, it can show the input graphic image mode and pixel clock frequency. 3.6.2 Memory Clock This clock is the synchronous clock for the external frame buffer. To accomplish the different DRAM types, configuration and bandwidth needed for various applications, the memory clock can be set from 50 MHz to 118 MHz by means of adjusting a set of appropriate values for M, N and R. The formula for calculating the desired frequency of the memory clock is as follows: fmclk = fosc5(M+2)/(N+2)51/R Where fmclk fosc M N R : the desired memory clock : oscillator clock with 14.31818 MHz : post-divider ratio : pre-divider ratio : optional divider ratio
3.6.3 Display Clock This clock is the synchronous clock for LCD panel. According to the LCD panel resolution of applications, the display clock range is from 50 MHz to 160 MHz by means of choosing a set of appropriate values for M, N as well as R. The computing formula is exactly the same as for the memory clock.
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4. REGISTER DESCRIPTION
INPUT CONTROL REGISTERS Address Mode Registers 00h R/W Input Image Vertical Active Line Start - Low 01h R/W Input Image Vertical Active Line Start - High 02h R/W Input Image Vertical Active Lines - Low 03h R/W Input Image Vertical Active Lines - High 04h 05h 06h 07h 10h 11h 12h 13h 14h 15h 16h 1Ah 1Ch 1Dh 1Fh 20h 21h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W Input Image Horizontal Active Pixel Start - Low Input Image Horizontal Active Pixel Start - High Input Image Horizontal Active Pixels - Low Input Image Horizontal Active Pixels - High Input Image Control Register 0 Input Image Control Register 1 Input Image Control Register 2 Input Image Control Register 3 Input Image Control Register 4 Input Image Control Register 5 Input Image Control Register 6 Input Delay Control 2 HS1 Sample Window Forward Extend HS1 Sample Window Backward Extend Input Image Status Register Input Image Back Porch Guard Band Input Image Front Porch Guard Band
MTL003
(Rev. 0.95)
Reset value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
FRAME SYNC REGISTERS Address Mode 28h R/W Frame Sync Control 2Ch 2Dh 2Eh 2Fh R/W R/W R/W R/W
Registers
Reset value 00h 00h 00h 00h 00h
Input Image Vertical Lock Position - Low Input Image Vertical Lock Position - High Input Image Horizontal Lock Position - Low Input Image Horizontal Lock Position - High
AUTO CALIBRATION REGISTERS Address Mode 30h R/W Auto Calibration Control 0 31h R/W Auto Calibration Control 1 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Revision 0.95 RO RO RO RO RO RO RO RO RO RO RO RO
Registers
Reset value 80h 00h 2000/06/14
Auto Calibration RED Value - Byte 0 Auto Calibration RED Value - Byte 1 Auto Calibration RED Value - Byte 2 Auto Calibration RED Value - Byte 3 Auto Calibration GREEN Value - Byte 0 Auto Calibration GREEN Value - Byte 1 Auto Calibration GREEN Value - Byte 2 Auto Calibration GREEN Value - Byte 3 Auto Calibration BLUE Value - Byte 0 Auto Calibration BLUE Value - Byte 1 Auto Calibration BLUE Value - Byte 2 Auto Calibration BLUE Value - Byte 3 - 22 -
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40h 41h 42h 43h 44h 45h 46h R/W R/W R/W R/W R/W R/W R/W Pixel Grab V Reference Position - Low Pixel Grab V Reference Position - High Pixel Grab H Reference Position - Low Pixel Grab H Reference Position - High Histogram Reference Color - RED Histogram Reference Color - GREEN Histogram Reference Color - BLUE
MTL003
(Rev. 0.95)
00h 00h 00h 00h 00h 00h 00h
SYNC PROCESSOR REGISTERS Address Mode 48h R/W SYNC Processor Control 49h R/W Auto Position Control 4Ah 4Bh 4Ch 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
Registers
Reset value 00h 00h 00h 00h 00h 00h 00h -
Auto Position Reference Color - RED Auto Position Reference Color - GREEN Auto Position Reference Color - BLUE Clamp Pulse Control 0 Clamp Pulse Control 1 Input VS Period Count by REFCLK - Low Input VS Period Count by REFCLK - High Input V Back Porch Count by Input HS - Low Input V Back Porch Count by Input HS - High Input V Active Lines Count by Input HS - Low Input V Active Lines Count by Input HS - High Input V Total Lines Count by Input HS - Low Input V Total Lines Count by Input HS - High Input HS Period Count by REFCLK - Low Input HS Period Count by REFCLK - High Input H Back Porch Count by Input Pixel Clock - Low Input H Back Porch Count by Input Pixel Clock - High Input H Active Pixels Count by Input Pixel Clock - Low Input H Active Pixels Count by Input Pixel Clock - High Input H Total Pixels Count by Input Pixel Clock - Low Input H Total Pixels Count by Input Pixel Clock - High
DISPLAY CONTROL REGISTERS Address Mode Registers 60h R/W Display Vertical Total - Low 61h R/W Display Vertical Total - High 62h R/W Display Vertical SYNC End- Low 63h R/W Display Vertical SYNC End - High 64h R/W Display Vertical Active Start - Low 65h R/W Display Vertical Active Start - High 66h R/W Display Vertical Active End - Low 67h R/W Display Vertical Active End - High 68h R/W Display Vertical Border Start - Low 69h R/W Display Vertical Border Start - High 6Ah R/W Display Vertical Border End - Low 6Bh R/W Display Vertical Border End - High 70h Revision 0.95 R/W Display Horizontal Total - Low - 23 -
Reset value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 2000/06/14
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71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 88h 89h 8Ah 90h 91h 92h 93h 94h 95h 96h 97h 98h 9Eh 9Fh A0h A1h A2h A4h A5h A6h A7h A9h AAh ABh ACh ADh AEh AFh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO Display Horizontal Total - High Display Horizontal SYNC End - Low Display Horizontal SYNC End - High Display Horizontal Active Start - Low Display Horizontal Active Start - High Display Horizontal Active End - Low Display Horizontal Active End - High Display Horizontal Border Start - Low Display Horizontal Border Start - High Display Horizontal Border End - Low Display Horizontal Border End - High Output Image Control Register 0 Output Image Control Register 1 Output Image Control Register 2 Color Gain Control - RED Color Gain Control - GREEN Color Gain Control - BLUE Brightness Control - RED Brightness Control - GREEN Brightness Control - BLUE Border Window Color - RED Border Window Color - GREEN Border Window Color - BLUE Dithering Table Data Port Gamma Table Data Port OSD Control Register 0 OSD Control Register 1 OSD Control Register 2 Output Invert Control Output Tri-State Control Output Clocks Delay Adjustment Output Clocks Duty Cycle Adjustment Output Miscellaneous Control Output Vertical Line Number - Low Output Vertical Line Number - High Output Horizontal Total Pixel Number - Low Output Horizontal Total Pixel Number - High Output Horizontal Total Residue Number - Low Output Horizontal Total Residue Number - High
MTL003
(Rev. 0.95)
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 80h 80h 80h 00h 00h 00h 00h 00h 00h 08h 00h 00h 00h 00h 00h 00h 00h FFh 02h -
ZOOM CONTROL REGISTERS Address Mode B0h R/W Zoom Control Register 0 B1h R/W Zoom Control Register 1 B2h B3h B4h B5h B6h B7h R/W R/W R/W R/W R/W R/W Zoom Zoom Zoom Zoom Zoom Zoom
Registers
Reset value 00h 00h 00h 00h 00h 00h 00h 00h
Vertical Scale Down Integer Horizontal Scale Down Integer Vertical Scale Ratio - Low Vertical Scale Ratio - High Horizontal Scale Ratio - Low Horizontal Scale Ratio - High
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BFh R/W Interpolation Table Data Port HOST CONTROL REGISTERS Address Mode C0h R/W Host Control Register 0 C1h R/W Host Control Register 1 C4h C5h C6h C7h C8h CBh R/W R/W R/W R/W R/W RO
MTL003
(Rev. 0.95)
-
Registers
Reset value 00h 00h 00h 03h 00h 00h 00h -
Host Screen Write Line Length - Low Host Screen Write Line Length - High Host Fill Color - RED Host Fill Color - GREEN Host Fill Color - BLUE Host Access Mode Status
MEMORY CONTROL REGISTERS Address Mode Registers D0h R/W Memory Type Control D2h R/W Memory Self Test Control D4h R/W Memory Line Offset - Low D5h R/W Memory Line Offset - High DBh DCh DDh RO RO RO Memory Self-Test Compare Error Address - Low Memory Self-Test Compare Error Address - Middle Memory Self-Test Compare Error Address - High
Reset value 00h 00h 00h 04h -
CLOCK CONTROL REGISTERS Address Mode E0h R/W Clock Control Register E1h E2h E3h E4h E5h E6h WO R/W R/W R/W R/W R/W
Registers
Reset value 00h 0Bh 32h 0Bh 32h 00h
Clock Synthesizer Value Load Display Clock Synthesizer N Value Display Clock Synthesizer M Value Memory Clock Synthesizer N Value Memory Clock Synthesizer M Value Clock Synthesizer R Value
INTERRUPT CONTROL REGISTERS Address Mode Registers E8h R/W SYNC Interrupt Flag Control E9h R/W General Interrupt Flag Control EAh R/W SYNC Interrupt Enable EBh R/W General Interrupt Enable ECh R/W HS Frequency Change interrupt Compare MISCELLANEOUS REGISTERS Address Mode Registers F1h R/W Power Management Control F4h R/W GPIO Control Register F5h R/W GPIO Direction Control F6h R/W GPIO Misc Control
Reset value 00h 00h 00h 00h 00h
Reset value 00h 00h 00h 00h
Input Image Vertical Active Line Start - Low (Address 00h) (R/W) It defines the low byte of the start position of the Vertical Active Window. Revision 0.95 - 25 2000/06/14
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D7-0 IV_ACT_START[7:0]
MTL003
(Rev. 0.95)
Input Image Vertical Active Line Start - High (Address 01h) (R/W) It defines the high byte of the start position of the Vertical Active Window. D7-3 D2-0 Reserved IV_ACT_START[10:8]
Input Image Vertical Active Lines - Low (Address 02h) (R/W) It defines the low byte of the number of active lines of the Vertical Active Window. D7-0 IV_ACT_LEN[7:0]
Input Image Vertical Active Lines - High (Address 03h) (R/W) It defines the high byte of the number of active lines of the Vertical Active Window. D7-3 D2-0 Reserved IV_ACT_LEN[10:8]
Input Image Horizontal Active Pixel Start - Low (Address 04h) (R/W) It defines the low byte of the start position of the Horizontal Active Window. D7-0 IH_ACT_START[7:0]
Input Image Horizontal Active Pixel Start - High (Address 05h) (R/W) It defines the high byte of the start position of the Horizontal Active Window. D7-3 D2-0 Reserved IH_ACT_START[10:8]
Input Image Horizontal Active Pixels - Low (Address 06h) (R/W) It defines the low byte of the number of active pixels of the Horizontal Active Window. D7-0 IH_ACT_WIDTH[7:0]
Input Image Horizontal Active Pixels - High (Address 07h) (R/W) It defines the high byte of the number of active pixels of the Horizontal Active Window. D7-3 D2-0 Reserved IH_ACT_WIDTH[10:8]
Input Image Control Register 0 (Address 10h) (R/W) D7 Horizontal Sampling Point Reference 0: from Input HSYNC. - 26 2000/06/14
Revision 0.95
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1: from Input HREF (only for Video Decoder). D6 Input YCBCR Format 0: 4-2-2 1: 4-1-1 Digital RGB 6 bit Mode 0: 8 bits 1: 6 bits Digital RGB Mode Select 0: RGB Input from ADC 1: RGB Input from Panel Link Input Image Format 0: RGB888 1: YCBCR Input Clock Source 0: from Graphic PLL clock. 1: from Video Decoder clock. Input Image Source 0: from Graphic source through ADC. 1: from Video source through Video Decoder like SAA7111A. ADC Configuration 0: Double Pixel mode 1: Single Pixel mode
MTL003
(Rev. 0.95)
D5
D4
D3
D2
D1
D0
Input Image Control Register 1 (Address 11h) (R/W) D7 D6-4 Reserved De-interlace mode Select 000: All Fields write mode 001: Toggle Field write mode 010: Spatial Filtering write mode Input YUV CCIR656 Format 0: Disable 1: Enable Reserved Still mode Enable 0: Live mode 1: Still mode
D3
D2-1 D0
Input Image Control Register 2 (Address 12h) (R/W) D7 Input ODD Field Invert 0: Normal 1: Invert External Input Interlace Select 0: Non-interlace - 27 2000/06/14
D6
Revision 0.95
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1: Interlace D5 External Input VSYNC Polarity 0: Active Low 1: Active High External Input HSYNC Polarity 0: Active Low 1: Active High Input ODD Field Source 0: from Internal Detection 1: from External pin. Input Interlace Source 0: from Internal detection 1: from Register setting (D6) Input VSYNC Polarity Source 0: from Internal detection 1: from Register setting (D5) Input HSYNC Polarity Source 0: from Internal detection 1: from Register setting (D4)
MTL003
(Rev. 0.95)
D4
D3
D2
D1
D0
Input Image Control Register 3 (Address 13h) (R/W) D7 Active Position Area for Auto Position in TMDS 0: from Internal Detection 1: from External Data Enable (TDIE) Reserved Sync On Green Select 0: Select Normal HSYNC/ Composite Sync 1: Select Sync On Green Input Vertical Timing based on VSYNC 0: Leading Edge 1: Trailing Edge Input Horizontal Timing based on HSYNC 0: Leading Edge 1: Trailing Edge
D6-3 D2
D1
D0
Input Image Control Register 4 (Address 14h) (R/W) D7 Input ODD Field Detection Point 0: at the start of VSYNC pulse. 1: at the end of VSYNC pulse. Input Image Port A, B Data and Clocks Swap 0: Normal 1: Swap Reserved - 28 2000/06/14
D6
D5 Revision 0.95
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D4 Input Image CBCR Order Swap 0: Normal 1: Swap Reserved
MTL003
(Rev. 0.95)
D3-0
Input Image Control Register 5 (Address 15h) (R/W) D7 Horizontal Pixel Valid Select 0: from Internal Programming 1: from External HREF/TDIE Reserved
D6-0
Input Image Control Register 6 (Address 16h) (R/W) D7-3 D2 Reserved ADC HS Polarity Invert when D1=1 0: Active Low 1: Active High Raw HS path Enable 0: Disable 1: Enable Reserved
D1
D0
Input Delay Control 2 (Address 1Ah) (R/W) D7-4 Input VSYNC Delay Adjustment 1111: 7 IDCLKs delay 1110: 6 IDCLKs delay 1101: 5 IDCLKs delay 1100: 4 IDCLKs delay 1011: 3 IDCLKs delay 1010: 2 IDCLKs delay 1001: 1 IDCLK delay 1000: Reserved 0111: 7ns gate delay 0110: 6ns gate delay 0101: 5ns gate delay 0100: 4ns gate delay 0011: 3ns gate delay 0010: 2ns gate delay 0001: 1ns gate delay 0000: No delay Input HSYNC Delay Adjustment 16 steps to change, each of them is 1ns delay/step.
D3-0
Input HS Pulse Width Forward Extend (Address 1Ch) (R/W) D7-0 Input HS Pulse Width Forward Extend by IDCLK HS1FWEXT[7:0]: Used when Interlace First/Second Field Detection.
Revision 0.95
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MYSON TECHNOLOGY
Input HS Pulse Width Backward Extend (Address 1Dh) (R/W) D7-0 Input HS Pulse Width Backward Extend by IDCLK HS1BWEXT[7:0]: Used when Interlace First/Second Field Detection.
MTL003
(Rev. 0.95)
Input Image Status Register (Address 1Fh) (RO) D7 Display VSYNC Monitor Show Display VSYNC signal directly. Input VSYNC Monitor Show Input VSYNC signal directly. External Input Interlace Status 0: Non-interlace 1: Interlace Extracted CVSYNC Present Status 0: Not Present 1: Present External Input VSYNC Present Status 0: Not Present 1: Present External Input HSYNC Present Status 0: Not Present 1: Present External Input VSYNC Polarity Status 0: Active Low 1: Active High External Input HSYNC Polarity Status 0: Active Low 1: Active High
D6
D5
D4
D3
D2
D1
D0
Input Image Back Porch Guard Band (Address 20h) (R/W) D7-0 Input Image Back Porch Guard Band by IDCLK HBPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
Input Image Front Porch Guard Band (Address 21h) (R/W) D7-0 Input Image Front Porch Guard Band by IDCLK HFPGB[7:0]: Used in Auto Position detection to mask out unwanted data.
Frame Sync Control 0 (Address 28h) (R/W) D7-5 D1 Reserved Frame Sync Select in Frame Buffer mode 0: Normal 1: Frame Sync Frame Buffer mode Select 0: Frame Buffer mode - 30 2000/06/14
D0
Revision 0.95
MYSON TECHNOLOGY
1: Non Frame Buffer mode Input Image Vertical Lock Position - Low (Address 2Ch) (R/W) It defines the low byte of the number of input lines where Display image timing synchronizes the input image source. D7-0 IPV_LOCK_POS[7:0]
MTL003
(Rev. 0.95)
Input Image Vertical Lock Position - High (Address 2Dh) (R/W) It defines the high byte of the number of input lines where Display image timing synchronizes the input image source. D7-3 D2-0 Reserved IPV_LOCK_POS[10:8]
Input Image Horizontal Lock Position - Low (Address 2Eh) (R/W) It defines the low byte of the number of input pixel clocks where Display image timing synchronizes the input image source. D7-0 IPH_LOCK_POS[7:0]
Input Image Horizontal Lock Position - High (Address 2Fh) (R/W) It defines the high byte of the number of input pixel clocks where Display image timing synchronizes the input image source. D7-3 D2-0 Reserved IPH_LOCK_POS[10:8]
Auto Calibration Control 0 (Address 30h) (R/W) D7 Pixel Grab Ready Flag (RO) 0: Ready 1: Not Ready Pixel Grab Update Enable 0: Stop updating 1: Continue updating Threshold Select Used in Histogram mode or MIN/MAX mode. 0: High bound / MAX 1: Low bound / MIN Phase Calibration Method Select 0: MYSON proprietary method 1: Difference Value method Auto Calibration Modes Select The measured value is available one item at a time, selected as shown: 00: Phase Calibration Mode - 31 2000/06/14
D6
D5
D4
D3-2
Revision 0.95
MYSON TECHNOLOGY
01: Histogram Mode 10: MIN/MAX Mode 11: Pixel Grab Mode D1 Auto Calibration Burst Mode Enable (except Pixel Grab Mode) 0: Single Mode 1: Burst Mode Auto Calibration Enable (W) (except Pixel Grab Value) 0: Disable 1: Enable Auto Calibration Ready Flag (R) 0: Ready 1: Not Ready
MTL003
(Rev. 0.95)
D0
Auto Calibration Control 1 (Address 31h) (R/W) D7-3 D2-0 Reserved Mask LSBs of Input Image Select It is used only for Phase Calibration to mask noise. 000: No Mask 001: Mask bit0 010: Mask bit0,1 011: Mask bit0,1,2 100: Mask bit0,1,2,3 101: Mask bit0,1,2,3,4 110: Mask bit0,1,2,3,4,5 111: Mask bit0,0,1,2,3,4,5,6
Auto Calibration RED Value - Byte 0 (Address 34h) (RO) It states the byte 0 of the number of Phase Calibration RED value in one frame or the byte 0 of the number of Histogram Red value in one frame or the Pixel Grab RED value in one frame of Non_interlace mode or FIRST field of Interlace mode. D7-0 CALVAL_R[7:0]
Auto Calibration RED Value - Byte 1 (Address 35h) (RO) It states the byte 1 of the number of Phase Calibration RED value in one frame or the byte 1 of the number of Histogram Red value in one frame or the Pixel Grab GREEN value in one frame of Non_interlace mode or FIRST field of Interlace mode. D7-0 CALVAL_R[15:8]
Auto Calibration RED Value - Byte 2 (Address 36h) (RO) It states the byte 2 of the number of Phase Calibration RED value in one frame or the byte 2 of the number of Histogram Red value in one frame or the Pixel Grab BLUE value in one frame of Non_interlace mode or FIRST field of Interlace mode. D7-0 CALVAL_R[23:16]
Auto Calibration RED Value - Byte 3 (Address 37h) (RO) Revision 0.95 - 32 2000/06/14
MYSON TECHNOLOGY
It states the byte 3 of the number of Phase Calibration RED value in one frame. D7-6 D5-0 Reserved CALVAL_R[29:24]
MTL003
(Rev. 0.95)
Auto Calibration GREEN Value - Byte 0 (Address 38h) (RO) It states the byte 0 of the number of Phase Calibration GREEN value in one frame or the byte 0 of the number of Histogram GREEN value in one frame or the Pixel Grab RED value in SECOND field of Interlace mode. D7-0 CALVAL_G[7:0]
Auto Calibration GREEN Value - Byte 1 (Address 39h) (RO) It states the byte 1 of the number of Phase Calibration GREEN value in one frame or the byte 1 of the number of Histogram GREEN value in one frame or the Pixel Grab GREEN value in SECOND field of Interlace mode. D7-0 CALVAL_G[15:8]
Auto Calibration GREEN Value - Byte 2 (Address 3Ah) (RO) It states the byte 2 of the number of Phase Calibration GREEN value in one frame or the byte 2 of the number of Histogram GREEN value in one frame or the Pixel Grab BLUE value in SECOND field of Interlace mode. D7-0 CALVAL_G[23:16]
Auto Calibration GREEN Value - Byte 3 (Address 3Bh) (RO) It states the byte 3 of the number of Phase Calibration GREEN value in one frame. D7-6 D5-0 Reserved CALVAL_G[29:24]
Auto Calibration BLUE Value - Byte 0 (Address 3Ch) (RO) It states the byte 0 of the number of Phase Calibration BLUE value in one frame or the byte 0 of the number of Histogram BLUE value in one frame or the MIN/MAX RED value in one frame. D7-0 CALVAL_B[7:0]
Auto Calibration BLUE Value - Byte 1 (Address 3Dh) (RO) It states the byte 1 of the number of Phase Calibration BLUE value in one frame or the byte 1 of the number of Histogram BLUE value in one frame or the MIN/MAX GREEN value in one frame. D7-0 CALVAL_B[15:8]
Auto Calibration BLUE Value - Byte 2 (Address 3Eh) (RO)
Revision 0.95
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MYSON TECHNOLOGY
It states the byte 2 of the number of Phase Calibration BLUE value in one frame or the byte 2 of the number of Histogram BLUE value in one frame or the MIN/MAX BLUE value in one frame. D7-0 CALVAL_B[23:16]
MTL003
(Rev. 0.95)
Auto Calibration BLUE Value - Byte 3 (Address 3Fh) (RO) It states the byte 3 of the number of Phase Calibration BLUE value in one frame. D7-6 D5-0 Reserved CALVAL_B[29:24]
Pixel Grab V Reference Position - Low (Address 40h) (R/W) It states the low byte of Vertical Reference Position in Pixel Grab Mode. D7-0 VGRAB_POS[7:0]
Pixel Grab V Reference Position - High (Address 41h) (R/W) It states the high byte of Vertical Reference Position in Pixel Grab Mode. D7-3 D2-0 Reserved VGRAB_POS[10:8]
Pixel Grab H Reference Position - Low (Address 42h) (R/W) It states the low byte of Horizontal Reference Position in Pixel Grab Mode. D7-0 HGRAB_POS[7:0]
Pixel Grab H Reference Position - High (Address 43h) (R/W) It states the high byte of Horizontal Reference Position in Pixel Grab Mode. D7-3 D2-0 Reserved HGRAB_POS[10:8]
Histogram Reference Color - RED (Address 44h) (R/W) It states the Histogram Reference RED Color in Histogram Mode. D7-0 HIST_R[7:0]
Histogram Reference Color - GREEN (Address 45h) (R/W) It states the Histogram Reference GREEN Color in Histogram Mode. D7-0 HIST_G[7:0]
Histogram Reference Color - BLUE (Address 46h) (R/W) It states the Histogram Reference BLUE Color in Histogram Mode. Revision 0.95 - 34 2000/06/14
MYSON TECHNOLOGY
D7-0 HIST_B[7:0]
MTL003
(Rev. 0.95)
SYNC Processor Control (Address 48h) (R/W) D7-2 D1-0 Reserved SYNC Source 00: from H/V SYNC 01: from CVSYNC (Composite SYNC) 1x: Auto switch to CVSYNC when CVSYNC is present, but VSYNC not.
Auto Position Control (Address 49h) (R/W) D7-2 D1 Reserved Auto Position Burst Mode Enable 0: Single Mode 1: Burst Mode Auto Position Enable (W) 0: Disable 1: Enable Auto Position Ready Flag (R) 0: Ready 1: Not Ready
D0
Auto Position Reference Color - RED (Address 4Ah) (R/W) It defines the red component color for selecting between black and non-black pixels. D7-0 REF_COLOR_RED[7:0]
Auto Position Reference Color - GREEN (Address 4Bh) (R/W) It defines the green component color for selecting between black and non-black pixels. D7-0 REF_COLOR_GREEN[7:0]
Auto Position Reference Color - BLUE (Address 4Ch) (R/W) It defines the blue component color for selecting between black and non-black pixels. D7-0 REF_COLOR_BLUE[7:0]
Clamp Pulse Control 0 (Address 4Eh) (R/W) D7 Clamp Pulse Mask 0: Normal 1: Mask out Clamp Pulse Clamp Pulse Start Reference Edge 0: From Input HSYNC trailing edge. 1: From Input HSYNC leading edge. Clamp Pulse output Polarity 0: Active High - 35 2000/06/14
D6
D5
Revision 0.95
MYSON TECHNOLOGY
1: Active Low D4-0
MTL003
(Rev. 0.95)
Clamp Pulse Start Start of Clamp Pulse after the selected edge of Input HSYNC by Input DCLK.
Clamp Pulse Control 1 (Address 4Fh) (R/W) D7-5 D4-0 Reserved Clamp Pulse Width To adjust Clamp Pulse Width by input DCLK.
Input VS Period Count by REFCLK - Low (Address 50h) (RO) It states the low byte of the number of REFCLK of the Vertical Sync period measurement. D7-0 VSPRD[7:0]
Input VS Period Count by REFCLK - High (Address 51h) (RO) It states the high byte of the number of REFCLK of the Vertical Sync period measurement. D7-4 D3-0 Reserved VSPRD[11:8]
Input V Back Porch Count by Input HS - Low (Address 52h) (RO) It states the low byte of the number of lines between the end of VSYNC and the active image. D7-0 VBPW[7:0]
Input V Back Porch Count by Input HS - High (Address 53h) (RO) It states the high byte of the number of lines between the end of VSYNC and the active image D7-3 D2-0 Reserved VBPW[10:8]
Input V Active Image Count by Input HS - Low (Address 54h) (RO) It states the low byte of the number of the active image lines. D7-0 VACTW[7:0]
Input V Active Image Count by Input HS - High (Address 55h) (RO) It states the high byte of the number of the active image lines D7-3 D2-0 Reserved VACTW[10:8]
Input V Total Image Count by Input HS - Low (Address 56h) (RO) It states the low byte of the number of the total image lines. Revision 0.95 - 36 2000/06/14
MYSON TECHNOLOGY
D7-0 VTOTW[7:0]
MTL003
(Rev. 0.95)
Input V Total Image Count by Input HS - High (Address 57h) (RO) It states the high byte of the number of the total image lines. D7-3 D2-0 Reserved VTOTW[10:8]
Input HS Period Count by REFCLK - Low (Address 58h) (RO) It states the low byte of the number of REFCLKs of the Horizontal Sync period measurement. D7-0 HSPRD[7:0]
Input HS Period Count by REFCLK - High (Address 59h) (RO) It states the high byte of the number of REFCLKs of the Horizontal Sync period measurement. D7-5 D4-0 Reserved HSPRD[12:8]
Input H Back Porch Count by Input Pixel Clock -Low (Address 5Ah) (RO) It states the low byte of the number of pixels between the end of HSYNC and the active image. D7-0 HBPW[7:0]
Input H Back Porch Count by Input Pixel Clock -High (Address 5Bh) (RO) It states the high byte of the number of pixels between the end of HSYNC and the active image. D7-3 D2-0 Reserved HBPW[10:8]
Input H Active Image Count by Input Pixel Clock-Low(Address 5Ch) (RO) It states the low byte of the number of the Horizontal active image pixels. D7-0 HACTW[7:0]
Input H Active Image Count by Input Pixel Clock-High(Address 5Dh)(RO) It states the high byte of the number of the Horizontal active image pixels. D7-3 D2-0 Reserved HACTW[10:8]
Input H Total Image Count by Input Pixel Clock- Low (Address 5Eh) (RO) It states the low byte of the number of the Horizontal total image pixels.
Revision 0.95
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MYSON TECHNOLOGY
D7-0 HTOTW[7:0] Input H Total Image Count by Input Pixel Clock- High (Address 5Fh) (RO) It states the high byte of the number of the Horizontal total image pixels. D7-3 D2-0 Reserved HTOTW[10:8]
MTL003
(Rev. 0.95)
Display Vertical Total - Low (Address 60h) (R/W) It defines the low byte of the number of lines per display frame. D7-0 DV_TOTAL[7:0]
Display Vertical Total - High (Address 61h) (R/W) It defines the high byte of the number of lines per display frame. D7-3 D2-0 Reserved DV_TOTAL[10:8]
Display Vertical SYNC End - Low (Address 62h) (R/W) It defines the low byte of Vertical SYNC end position in lines. D7-0 DV_SYNC_END[7:0]
Display Vertical VSYNC End - High (Address 63h) (R/W) It defines the high byte of Vertical SYNC end position in lines. D7-3 D2-0 Reserved DV_SYNC_END[10:8]
Note: Display Vertical SYNC Start is always equal 0. Display Vertical Active Start - Low (Address 64h) (R/W) It defines the low byte of Vertical Active region start position in lines. D7-0 DV_ACT_START[7:0]
Display Vertical Active Start - High (Address 65h) (R/W) It defines the high byte of Vertical Active region start position in lines. D7-3 D2-0 Reserved DV_ACT_START[10:8]
Display Vertical Active End - Low (Address 66h) (R/W) It defines the low byte of Vertical Active region end position in lines. Revision 0.95 - 38 2000/06/14
MYSON TECHNOLOGY
D7-0 DV_ACT_END[7:0]
MTL003
(Rev. 0.95)
Display Vertical Active End - High (Address 67h) (R/W) It defines the high byte of Vertical Active region end position in lines. D7-3 D2-0 Reserved DV_ACT_END[10:8]
Display Vertical Border Start - Low (Address 68h) (R/W) It defines the low byte of Vertical Border start position in lines. D7-0 DV_BOR_START[7:0]
Display Vertical Border Start - High (Address 69h) (R/W) It defines the high byte of Vertical Border start position in lines. D7-3 D2-0 Reserved DV_BOR_START[10:8]
Display Vertical Border End - Low (Address 6Ah) (R/W) It defines the low byte of Vertical Border end position in lines. D7-0 DV_BOR_END[7:0]
Display Vertical Border End - High (Address 6Bh) (R/W) It defines the high byte of Vertical Border end position in lines. D7-3 D2-0 Reserved DV_BOR_END[10:8]
Display Horizontal Total - Low (Address 70h) (R/W) It defines the low byte of the number of display clock cycles per display line. D7-0 DH_TOTAL[7:0]
Display Horizontal Total - High (Address 71h) (R/W) It defines the high byte of the number of display clock cycles per display line. D7-3 D2-0 Reserved DH_TOTAL[10:8]
Display Horizontal SYNC End - Low (Address 72h) (R/W) It defines the low byte of Horizontal SYNC end position in display clock cycles.
Revision 0.95
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MYSON TECHNOLOGY
D7-0 DH_SYNC_END[7:0] Display Horizontal SYNC End - High (Address 73h) (R/W) It defines the high byte of Horizontal SYNC end position in display clock cycles. D7-3 D2-0 Reserved DH_SYNC_END[10:8]
MTL003
(Rev. 0.95)
Note: Display Horizontal SYNC Start is always equal 0. Display Horizontal Active Start - Low (Address 74h) (R/W) It defines the low byte of Horizontal Active region start position in display clock cycles. D7-0 DH_ACT_START[7:0]
Display Horizontal Active Start - High (Address 75h) (R/W) It defines the high byte of Horizontal Active region start position in display clock cycles. D7-3 D2-0 Reserved DH_ACT_START[10:8]
Display Horizontal Active End - Low (Address 76h) (R/W) It defines the low byte of Horizontal Active region end position in display clock cycles. D7-0 DH_ACT_END[7:0]
Display Horizontal Active End - High (Address 77h) (R/W) It defines the high byte of Horizontal Active region end position in display clock cycles. D7-3 D2-0 Reserved DH_ACT_END[10:8]
Display Horizontal Border Start - Low (Address 78h) (R/W) It defines the low byte of Horizontal Border start position in display clock cycles. D7-0 DH_BOR_START[7:0]
Display Horizontal Border Start - High (Address 79h) (R/W) It defines the high byte of Horizontal Border start position in display clock cycles. D7-3 D2-0 Reserved DH_BOR_START[10:8]
Display Horizontal Border End - Low (Address 7Ah) (R/W) It defines the low byte of Horizontal Border end position in display clock cycles. Revision 0.95 - 40 2000/06/14
MYSON TECHNOLOGY
D7-0 DH_BOR_END[7:0]
MTL003
(Rev. 0.95)
Display Horizontal Border End - High (Address 7Bh) (R/W) It defines the high byte of Horizontal Border end position in display clock cycles. D7-3 D2-0 Reserved DH_BOR_END[10:8]
Output Image Control Register 0 (Address 88h) (R/W) D7-3 D2 Reserved Output Pixel 18 bit RGB Mode Select 0: 24 bit RGB 1: 18 bit RGB Output Dual Pixel Data Exchange 0: Normal 1: Exchange Output Dual Pixel Select 0: Dual Pixel 1: Single Pixel
D1
D0
Output Image Control Register 1 (Address 89h) (R/W) D7-6 D5 Reserved RGB Brightness Control Enable 0: Disable 1: Enable RGB Gain Control Enable 0: Disable 1: Enable Reserved Border Window Function 0: OFF 1: ON Output Blank Screen 0: Normal 1: Output Pixel masked as BLACK color
D4
D3-2 D1
D0
Output Image Control Register 2 (Address 8Ah) (R/W) D7 D6 Reserved Temporal Dithering Enable 0: Static Dithering 1: Temporal Dithering
Revision 0.95
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MYSON TECHNOLOGY
D5 Dithering Table R/W Access Enable 0: Disable 1: Enable Dithering Enable 0: Disable 1: Enable Reserved 10 bit Gamma Table Enable 0: 8 bit Gamma Table 1: 10 bit Gamma Table Gamma Table R/W Access Enable 0: Disable 1: Enable Gamma Correction Function 0: OFF 1: ON
MTL003
(Rev. 0.95)
D4
D3 D2
D1
D0
Color Gain Control - RED (Address 90h) (R/W) It can be used to adjust the gain of RED component of the Display Image. D7-0 RGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Gain Control - GREEN (Address 91h) (R/W) It can be used to adjust the gain of GREEN component of the Display Image. D7-0 GGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Gain Control - BLUE (Address 92h) (R/W) It can be used to adjust the gain of BLUE component of the Display Image. D7-0 BGAIN[7:0] 0(00h) ~ x1(80h) ~ x1.992185(FFh)
Color Brightness Control - RED (Address 93h) (R/W) It can be used to adjust the brightness of RED component of the Display Image. D7-0 RBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
Color Brightness Control - GREEN (Address 94h) (R/W) It can be used to adjust the brightness of GREEN component of the Display Image. D7-0 GBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
Revision 0.95
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MYSON TECHNOLOGY
Color Brightness Control - BLUE (Address 95h) (R/W) It can be used to adjust the brightness of BLUE component of the Display Image. D7-0 BBRIGHT[7:0] -128(80h) ~ 0(00h) ~127(7Fh)
MTL003
(Rev. 0.95)
Border Window Color - RED (Address 96h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the RED component of the border color. D7-0 BCR[7:0]
Border Window Color - GREEN (Address 97h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the GREEN component of the border color. D7-0 BCG[7:0]
Border Window Color - BLUE (Address 98h) (R/W) When the Display Image is not expanded to full screen, it can be specified as the BLUE component of the border color. D7-0 BCB[7:0]
Dithering Table Data Port (Address 9Eh) (R/W) Since the Dithering Table is downloadable, this data port is the entry address. D7-0 DITHER_PORT[7:0]
Gamma Table Data Port (Address 9Fh) (R/W) Since the Gamma Table is downloadable, this data port is the entry address. D7-0 GAMMA_PORT[7:0]
OSD Control Registers (Address A0h) (R/W) D7 OSD Output Clock Select 0: from Internal Display Dot Clock 1: from Internal Display Dot Clock x 2 OSD Output VS Invert 0: Normal 1: Invert Reserved OSD Function 0: OFF 1: ON OSD Intensity Enable (For MOTOROLA) - 43 2000/06/14
D6
D5-4 D3
D2 Revision 0.95
MYSON TECHNOLOGY
0: Disable 1: Enable D1-0 OSD TYPE Select 00: OSDRGB = {R0000000, G0000000, B0000000} 01: OSDRGB = {RR000000, GG000000, BB000000} 10: OSDRGB = {RRRR0000, GGGG0000, BBBB0000} 11: OSDRGB = {RRRRRRRR, GGGGGGGG, BBBBBBBB} R = OSDR, G = OSDG, B = OSDB
MTL003
(Rev. 0.95)
OSD Control Register 1 (Address A1h) (R/W) D7 OSD Output HS Invert 0: Normal 1: Invert. OSD Output DCLK Invert 0: Normal 1: Invert. OSD Output HS Delay 4 steps to change, each of them is 1ns delay/step. OSD Input Data Sample Clock Invert 0: Normal. 1: Invert. OSD Input Data Sample Clock Delay 8 steps to change, each of them is 1ns delay/step.
D6
D5-4
D3
D2-0
OSD Control Register 2 (Address A2h) (R/W) D7-4 D3-0 Reserved OSD Output Clock Delay 16 steps to change, each of them is 1ns delay/step.
Output Invert Control (Address A4h) (R/W) D7 D6 Reserved RGB Data Invert Enable 0: Disable 1: Enable Display DCLK2 Invert 0: Normal 1: Invert Display DCLK1 Invert 0: Normal 1: Invert Reserved Display Data Enable (DDEN) Invert 0: Normal - 44 2000/06/14
D5
D4
D3 D2
Revision 0.95
MYSON TECHNOLOGY
1: Invert D1 Display VSYNC Invert 0: Normal 1: Invert Display HSYNC Invert 0: Normal 1: Invert
MTL003
(Rev. 0.95)
D0
Output Tri_state Control (Address A5h) (R/W) D7 Display Data R2OUT, G2OUT, B2OUT Output Disable 0: Normal 1: Tri_stated Display Data R1OUT, G1OUT, B1OUT Output Disable 0: Normal 1: Tri_stated Display DCLK2 Output Disable 0: Normal 1: Tri_stated Display DCLK1 Output Disable 0: Normal 1: Tri_stated OSD OCLK / OVSYNC / OHSYNC Output Disable 0: Normal 1: Tri_stated Display Data Enable (DDEN) Output Disable 0: Normal 1: Tri_stated Display VSYNC Output Disable 0: Normal 1: Tri_stated Display HSYNC Output Disable 0: Normal 1: Tri_stated
D6
D5
D4
D3
D2
D1
D0
Output Clocks Delay Adjustment (Address A6h) (R/W) D7-4 Display DCLK2 delay adjustment 16 steps to adjust, Typical 1ns delay/step Display DCLK1 delay adjustment 16 steps to adjust, Typical 1ns delay/step
D3-0
Output Clocks Duty Cycle Adjustment (Address A7h) (R/W) D7 Display DCLK2 duty cycle Increase/Decrease 0: Decrease 1: Increase - 45 2000/06/14
Revision 0.95
MYSON TECHNOLOGY
D6-4 Display DCLK2 duty cycle adjustment 8 steps to adjust, Typical 0.5ns delay/step Display DCLK1 duty cycle Increase/Decrease 0: Decrease 1: Increase Display DCLK1 duty cycle adjustment 8 steps to adjust, Typical 0.5ns delay/step
MTL003
(Rev. 0.95)
D3
D2-0
Output Miscellaneous Control (Address A9h) (R/W) D7 Second field Line Buffer Overflow status for Interlace input (RO) 0: Not Overflow 1: Overflow Second field Line Buffer Underflow status for Interlace input (RO) 0: Not Underflow 1: Underflow First field Line Buffer Overflow status for Interlace input or Line buffer Overflow status for Non-interlace input (RO) 0: Not Overflow 1: Overflow First field Line Buffer Underflow status for Interlace input or Line Buffer Overflow status for Non-interlace input (RO) 0: Not Underflow 1: Underflow Auto Output Horizontal Total Calculation Start (W) 0: Disable 1: Enable Auto Output Horizontal Total Calculation Ready Flag (R) 0: Ready 1: Not Ready Reserved
D6
D5
D4
D3
D2-0
Output Vertical Active Line Number - Low (Address AAh) (R/W) It defines the low byte of Output Vertical Active Line Number only used for getting the values of Reg. ACh and ADh. D7-0 OVDE[7:0]
Output Vertical Active Line Number - High (Address ABh) (R/W) It defines the high byte of Output Vertical Active Line Number only used for getting the values of Reg. ACh and ADh. D1-0 OVDE[9:8]
Output Horizontal Total Pixel Number - Low (Address ACh) (RO) It states the low byte of Output Horizontal Total Pixel Number. Revision 0.95 - 46 2000/06/14
MYSON TECHNOLOGY
D7-0 OHTOT[7:0]
MTL003
(Rev. 0.95)
Output Horizontal Total Pixel Number - High (Address ADh) (RO) It states the high byte of Output Horizontal Total Pixel Number. D2-0 OHTOT[10:8]
Output Horizontal Total Residue Number - Low (Address AEh) (RO) It states the low byte of Output Horizontal Total Pixel Residue Number. D7-0 OHTOT_RES[7:0]
Output Horizontal Total Residue Number - High (Address AFh) (RO) It states the high byte of Output Horizontal Total Pixel Residue Number. D7-2 D1-0 Reserved OHTOT_RES[9:8]
Zoom Control Register 0 (Address B0h) (R/W) D7 Vertical Scale Mode 0: Scale Up 1: Scale Down Vertical Scale Select 0XX: PASS mode 10X: DUPLICATE mode 110: BILINEAR mode 111: INTERPOLATION TABLE mode (only for Scale Up) Horizontal Scale Mode 0: scale up 1: scale down Horizontal Scale Select 0xx: PASS mode 10x: DUPLICATE mode 110: BILINEAR mode 111: INTERPOLATION TABLE mode
D6-4
D3
D2-0
Zoom Control Register 1 (Address B1h) (R/W) D7-1 D0 Reserved Interpolation Table R/W Access Enable 0: Disable 1: Enable
Zoom Vertical Scale Down Integer Ratio Region (Address B2h) (R/W) It defines vertical scale down integer ratio value region
Revision 0.95
- 47 -
2000/06/14
MYSON TECHNOLOGY
D7-3 D2-0 Reserved ZVDIV[2:0] 0 : scale down ratio = 1-1/2(exclude 1) 1 : scale down ratio = 1/2-1/4(exclude 1/2) 2: scale down ratio = 1/4-1/8(exclude 1/4) 3: scale down ratio = 1/8-1/16(exclude 1/8) 4: scale down ratio = 1/16-1/32(exclude 1/16)
MTL003
(Rev. 0.95)
Zoom Horizontal Scale Down Integer Ratio Region (Address B3h) (R/W) It defines horizontal scale down integer ratio value region. D7-3 D2-0 Reserved ZHDIV[2:0] 0 : scale down ratio = 1-1/2(exclude 1) 1 : scale down ratio = 1/2-1/4(exclude 1/2) 2: scale down ratio = 1/4-1/8(exclude 1/4) 3: scale down ratio = 1/8-1/16(exclude 1/8) 4: scale down ratio = 1/16-1/32(exclude 1/16)
Zoom Vertical Scale Ratio - Low (Address B4h) (R/W) It defines the low byte of vertical scale ratio value for scale up and down. D7-0 ZVSF[7:0]
Zoom Vertical Scale Ratio - High (Address B5h) (R/W) It defines the low byte of vertical scale ratio value for scale up and down. D7-0 ZVSF[15:8]
For Scale Up ZVSF = CEIL[(input_height - 1)/ (output_height - 1)* 216] For Scale Down ZVSF = CEIL{[(input_height'- 1)/ (output_height - 1)-1]* 216} ,where input_height'= input_height / 2^ZVDIV. The means of ZVDIV is referenced to Reg. B2h. Zoom Horizontal Scale Ratio - Low (Address B6h) (R/W) It defines the low byte of horizontal scale ratio value for scale up and down. D7-0 ZHSF[7:0]
Zoom Horizontal Scale Ratio - High (Address B7h) (R/W) It defines the high byte of horizontal scale ratio value for scale up and down. D7-0 ZHSF[15:8]
For Scale Up ZHSF = ROUND[(input_width - 1)/ (output_width - 1)* 216] For Scale Down ZVSF = ROUND{[(input_width'- 1)/ (output_width - 1)-1]* 216} ,where input_width'= input_width / 2^ZHDIV. The means of ZHDIV is referenced to Reg. B3h. Interpolation Table Data Port (Address BFh) (R/W) It defines the entry address of the Interpolation table data port. Revision 0.95 - 48 2000/06/14
MYSON TECHNOLOGY
D7-0 TFPORT[7:0]
MTL003
(Rev. 0.95)
Host Control Register 0 (Address C0h) (R/W) D7 Host Screen Write Stop Enable (WO) 0: Disable 1: Enable Force to 001010 Host Screen Write Start Enable (W) 0: Disable 1: Enable Host Screen Write Ready Flag (R) 0: Ready 1: Not Ready
D6-1 D0
Host Control Register 1 (Address C1h) (R/W) D7 D6 Reserved I2C Bus Address No Increment 0: Normal 1: No Increment Double Buffer load Select 0: Immediately 1: Delay to Display VSYNC Registers Double Buffer function Enable 0: Disable 1: Enable Reserved Display Registers Double Buffer Load (WO) Input Registers Double Buffer Load (WO)
D5
D4
D3-2 D1 D0
Host Screen Write Line Length - Low (Address C4h) (R/W) It defines the low byte of the vertical line length for Host Screen Write. D7-0 HS_LEN[7:0]
Host Screen Write Line Length - High (Address C5h) (R/W) It defines the high byte of the vertical line length for Host Screen Write. D7-3 D2-0 Reserved HS_LEN[10:8]
Host Fill RED Color (Address C6h) (R/W) It defines Fill Red color for Host Screen Write. Revision 0.95 - 49 2000/06/14
MYSON TECHNOLOGY
D7-0 HFR[7:0]
MTL003
(Rev. 0.95)
Host Fill GREEN Color (Address C7h) (R/W) It defines Fill Green color for Host Screen Write. D7-0 HFG[7:0]
Host Fill BLUE Color (Address C8h) (R/W) It defines Fill Blue color for Host Screen Write. D7-0 HFB[7:0]
Host Access Mode Status (Address CBh) (RO) D7-1 D0 Reserved Host Access Mode 0: 2-wire Serial mode (IIC) 1: 8-bit Parallel mode
Memory Type Control (Address D0h) (R/W) D7-5 D4 Reserved 32 bits Memory Bus (Only for X2 Memory Configuration) 0: Disable 1: Enable Reserved 000: 16M SDRAM X 3 001: 16M SDRAM X 2 010: 8M SGRAM X 3 011: 8M SGRAM X 2 10x: Reserved 110: 16M SGRAM X 3 111: 16M SGRAM X 2
D3 D2-0
Memory Self Test Control (Address D2h) (R/W) It controls the operation of Memory Self Test Mode. D7-3 D2 Reserved Memory Self Test mode Result Status (RO) 0: Success 1: Fail Memory Self Test mode Finish Status (RO) 0: Finish 1: Not Finish Memory Self Test mode Enable 0: Disable - 50 2000/06/14
D1
D0
Revision 0.95
MYSON TECHNOLOGY
1: Enable Memory Line Offset - Low (Address D4h) (R/W) It defines the low byte of Memory Line Offset Address Length for Memory Read/Write. D7-0 Line_offset[7:0]
MTL003
(Rev. 0.95)
Memory Line Offset - High (Address D5h) (R/W) It defines the high byte of Memory Line Offset Address Length for Memory Read/Write. D7-3 D2-0 Reserved Line_offset[10:8]
Memory Self-Test Compare Error Address - Low (Address DBh) (RO) It defines the low byte of Memory Base Address for Memory Self-Test comparing error report. D7-0 MSFTBA [7:0]
Memory Self-Test Compare Error Address - Middle (Address DCh) (RO) It defines the middle byte of Memory Base Address for Memory Self-Test comparing error report. D7-0 MSFTBA [15:8]
Memory Self-Test Compare Error Address - High (Address DDh) (RO) It defines the high byte of Memory Base Address for Memory Self-Test comparing error report and Patterns Number. D7 D6-5 Reserved Memory Self-Test Patterns Number when Comparing Error 00: Pattern Constructed by Linear Memory Address 01: 48 Bits Pattern Toggled between 55 and AA 10: 48 Bits Pattern Toggled between AA and 55 11: Reserved MSFTBA [20:16]
D4-0
Clock Synthesizer Control Register (Address E0h) (R/W) D7-4 D3 Reserved Memory Clock Source 0: Internal Memory Clock 1: External Memory Clock from pin EXTMCLK Display Clock Source 0: Internal Display Clock 1: External Display Clock from pin EXTDCLK Memory Clock Synthesizer Enable 0: Enable - 51 2000/06/14
D2
D1
Revision 0.95
MYSON TECHNOLOGY
1: Disable D0 Display Clock Synthesizer Enable 0: Enable 1: Disable
MTL003
(Rev. 0.95)
Clock Synthesizer Value Load (Address E1h) (WO) D7-2 D1 D0 Reserved Memory Clock Synthesizer Value Load (WO) Display Clock Synthesizer Value Load (WO)
Display Clock Synthesizer N Value (Address E2h) (R/W) D7-0 Display Clock Synthesizer N value
Display Clock Synthesizer M Value (Address E3h) (R/W) D7-0 Display Clock Synthesizer M value
Memory Clock Synthesizer N Value (Address E4h) (R/W) D7-0 Memory Clock Synthesizer N value
Memory Clock Synthesizer M Value (Address E5h) (R/W) D7-0 Memory Clock Synthesizer M value
Clock Synthesizer R Value (Address E6h) (R/W) D7-4 D3-2 Reserved Memory Clock Synthesizer R value 00: No divided 01: Divided by 2 1x: Divided by 4 Display Clock Synthesizer R value 00: No divided 01: Divided by 2 1x: Divided by 4
D1-0
SYNC Interrupt Flag Control (Address E8h) (R) It contains the status of SYNC Interrupts. D7 Display VSYNC Pulse Interrupt Status 0: No Display VSYNC pulse detected 1: Any Display VSYNC pulse detected Input VSYNC Pulse Interrupt Status 0: No Input VSYNC pulse detected 1: Any Input VSYNC pulse detected VSYNC Presence Change Status - 52 2000/06/14
D6
D5 Revision 0.95
MYSON TECHNOLOGY
0: No Change 1: Change D4 HSYNC Presence Change Status 0: No Change 1: Change VSYNC Polarity Change Status 0: No Change 1: Change HSYNC Polarity Change Status 0: No Change 1: Change VSYNC Frequency Change Status 0: No Change 1: Change HSYNC Frequency Change Status 0: No Change 1: Change
MTL003
(Rev. 0.95)
D3
D2
D1
D0
SYNC Interrupt Flag Control (Address E8h) (W) It is used to clear the corresponding SYNC interrupt signal when Software finishes serving the interrupt service routine. D7 Clear Display VSYNC Pulse Interrupt Enable 0: Disable 1: Enable Clear Input VSYNC Pulse Interrupt Enable 0: Disable 1: Enable Clear VSYNC Presence Change Interrupt Enable 0: Disable 1: Enable Clear HSYNC Presence Change Interrupt Enable 0: Disable 1: Enable Clear VSYNC Polarity Change Interrupt Enable 0: Disable 1: Enable Clear HSYNC Polarity Change Interrupt Enable 0: Disable 1: Enable Clear VSYNC Frequency Change Interrupt Enable 0: Disable 1: Enable Clear HSYNC Frequency Change Interrupt Enable 0: Disable - 53 2000/06/14
D6
D5
D4
D3
D2
D1
D0 Revision 0.95
MYSON TECHNOLOGY
1: Enable General Interrupt Flag Control (Address E9h) (R) It contains the status of General Interrupts. D7-2 D1 Reserved Auto Position Finish Status (valid for Single mode only) 0: Not Finish 1: Finish Auto Calibration Finish Status (valid for Single mode only) 0: Not Finish 1: Finish
MTL003
(Rev. 0.95)
D0
General Interrupt Flag Control (Address E9h) (W) It is used to clear the corresponding general interrupt signal when Software finishes serving the interrupt service routine. D7-2 D1 Reserved Clear Auto Position Finish Interrupt Enable 0: Disable 1: Enable Clear Auto Calibration Finish Interrupt Enable 0: Disable 1: Enable
D0
SYNC Interrupt Flag Enable (Address EAh) (R/W) It is used to enable SYNC Interrupt function. D7 Display VSYNC Pulse Interrupt Enable 0: Disable 1: Enable Input VSYNC Pulse Interrupt Enable 0: Disable 1: Enable VSYNC Presence Change Interrupt Enable 0: Disable 1: Enable HSYNC Presence Change Interrupt Enable 0: Disable 1: Enable VSYNC Polarity Change Interrupt Enable 0: Disable 1: Enable HSYNC Polarity Change Interrupt Enable 0: Disable - 54 2000/06/14
D6
D5
D4
D3
D2
Revision 0.95
MYSON TECHNOLOGY
1: Enable D1 VSYNC Frequency Change Interrupt Enable 0: Disable 1: Enable HSYNC Frequency Change Interrupt Enable 0: Disable 1: Enable
MTL003
(Rev. 0.95)
D0
General Interrupt Flag Enable (Address EBh) (R/W) It is used to enable General Interrupt functions. D7 Interrupt Output Polarity Invert 0: Active Low 1: Active High Reserved Auto Position Finish Interrupt Enable 0: Disable 1: Enable Auto Calibration Finish Interrupt Enable 0: Disable 1: Enable
D6-2 D1
D0
HS Frequency Change Interrupt Compare (Address ECh) (R/W) It is used to control Interrupt generation by comparing the frequency change value when Input HS Frequency Changes. D7-0 HSCMPREG[7:0]
Power Management Control (Address F1h) (R/W) D7 D6 Reserved Power Down Gamma & Interpolation Table 0: Normal 1: Power Down Power Down Output Line Buffers 0: Normal 1: Power Down Power Down Input Line Buffers 0: Normal 1: Power Down Reserved Power Down all the clocks except REFCLK 0: Normal 1: Power Down
D5
D4
D3-2 D1
Revision 0.95
- 55 -
2000/06/14
MYSON TECHNOLOGY
D0 Software Reset Enable 0: Disable 1: Enable
MTL003
(Rev. 0.95)
GPIO Control Register (Address F4h) (R/W) It controls the data of the GPIO pins. D7-0 GPIO[7:0]
GPIO Direction Control (Address F5h) (R/W) It controls the In/Out direction of the GPIO pins, where "0" means Output, and "1" means Tri_state or Input. D7-6 GPIO[7:6] Output Enable 0: Output 1: Tri_state GPIO[5:0] In/Out Select 0: Output 1: Input
D5-0
GPIO Misc Control (Address F6h) (R/W) It defines the GPIO pins miscellaneous control. D7-1 D0 Reserved GPIO[7:6] Output Pins Source 0: from Reg. F4h/D7-6 1: from ADVS/ADHS
Revision 0.95
- 56 -
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MYSON TECHNOLOGY
5. ELECTRICAL CHARACTERISTICS 5.1 DC CHARACTERISTICS
MTL003
(Rev. 0.95)
Table 5.1 Recommended Operating Conditions SYMBOL Vcc Tamb Tstg PARAMETER Operation Voltage Operating Ambient Temperature Storage Temperature MIN 3.0 0 -55 TYP 3.3 MAX 3.6 70 150 UNIT V o C o C
Table 5.2 DC Electrical Characteristics for 3.3 V Operation SYMBOL VIL VIH VtPARAMETER CONDITIONS Input Low Voltage Input High Voltage Input Schmitt Trigger Low Voltage at pins SDA and SCK Input Schmitt Trigger High Voltage at pins SDA and SCK Output Low Voltage Output High Voltage Input Pull-up/Down VIL = 0v or Resistance VIH = VCC Input Leakage Current Output Leakage Current MIN 2.0 1.0 TYP MAX 0.8 UNIT V V
Vt+
1.7
VOL VOH RI ILI ILO
0.4 2.4 75 -10 -20 10 20
V V Kohm uA uA
Revision 0.95
- 57 -
2000/06/14
MYSON TECHNOLOGY
5.2 AC CHARACTERISTICS
MTL003
(Rev. 0.95)
Input Interface Timing
Figure 5.2.1 Input Interface Timing
IPCLK
Input VS/HS
Tivhs Tivhh
PIXIN[23:0]
Tids Tidh
Table 5.2.1 Input Interface Timing
SYMBOL Tids Tidh Tivhs Tivhh
PARAMETER Input Image Signal Setup Time for IPCLK Input Image Signal Hold Time for IPCLK Input VSYNC/HSYNC Setup Time for IPCLK Input VSYNC/HSYNC Hold Time for IPCLK
MIN 2 3 2 3
MAX
UNIT ns ns ns ns
Revision 0.95
- 58 -
2000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
Output Interface Timing
Figure 5.2.2 Output Interface Timing
Tdck
DDCLK
Tdvs
Display VS
Tdhs
Display HS
Tdde
Display DDEN
Tddp
PIXOUT1[23:0] / PIXOUT2[23:0]
Table 5.2.2 Output Interface Timing
SYMBOL Tdck Tdvs Tdhs Tdde Tddp
PARAMETER Display Clock DDCLK Frequency Display VSYNC Output Delay to DDCLK Display HSYNC Output Delay to DDCLK Display DDEN Output Delay to DDCLK Display Data Output Delay to DDCLK
MIN 9 2 0.5 1 1.5
MAX
UNIT ns ns ns ns ns
Note: DDCLK phase can be adjusted relative to data and control outputs using the DDCLK_INV (Reg. A4h/D5-4) and DDCLK_DELAY[2:0] (Reg. A6h/D7-0) programming controls.
Revision 0.95
- 59 -
2000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
OSD Interface Timing
Figure 5.2.3 OSD Interface Timing
OCLK
Tosdd
OVSYNC / OHSYNC
Input OSDDEN / OSDRED / OSDGRN / OSDBLU
Tosds Tosdh
Table 5.2.3 OSD Interface Timing
SYMBOL Tosdd Tosds Tosdh
PARAMETER OSD VS / HS Output Delay to OCLK OSD Signal Input Setup Time for OCLK OSD Signal Input Hold Time for OCLK
MIN 2 5.5 0
MAX
UNIT ns ns ns
Note: OCLK phase can be adjusted using OCLK_INV (Reg. A1h/D3) programming control and OHSYNC phase can be adjusted using OHSYNC_DELAY[1:0] (Reg. A1h/D5-4) programming control.
Revision 0.95
- 60 -
2000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
I2C Host Interface Timing
Figure 5.2.4 I C Host Interface Timing
Thigh
2
Tsu:sta
Tlow
Thd:sto
Thd:sta
Tsu:dat
Thd:dat
Tsu:sto
Table 5.2.4 I C Host Interface Timing
2
SYMBOL Thigh Tlow Tsu:dat Thd:dat Tsu:sta Thd:sta Tsu:sto Thd:sto
PARAMETER Clock High Period Clock Low Period Data in Setup Time Data in Hold Time Start condition Setup Time Start condition Hold Time Stop condition Setup Time Stop condition Hold Time
MIN 500 500 200 100 500 500 500 500
MAX
UNIT ns ns ns ns ns ns ns ns
Revision 0.95
- 61 -
2000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
8-bit Direct Host Interface Timing
Figure 5.2.5 8-bit Direct Host Interface Timing
ALE
Tllwl
Trwpw
Twhlh
WR/RD
Tavll Tllax Tqvwh
AD(7:0)/WR
A0-A7
DATA IN
AD(7:0)/RD
A0-A7
DATA OUT
Trlaz
Trldv
Trhdz
h h h Table 5.2.5 8-bit Direct Host Interface Timing
SYMBOL Tavll Tllax Trwpw Tllwl Tqvwh Twhqx Twhlh Trlaz Trldv Trhdz
PARAMETER Address Valid to ALE Low Address Hold After ALE Low WR/RD Pulse Width ALE Low to WR/RD Low Data Valid to WR High Data Hold After WR WR/RD High to ALE High RD Low to Address Float RD Low to Valid Data In Data Float after RD High
MIN 3 5 35 5 3 10 0 -5 0
MAX
30 15
UNIT ns ns ns ns ns ns ns ns ns ns
Revision 0.95
- 62 -
2000/06/14
MYSON TECHNOLOGY
MTL003
(Rev. 0.95)
Memory Interface (SDRAM/SGRAM) Timing
Figure 5.2.6 Memory Interface Timing
Tmck Tmch
MCK
Tmds Tmdh
MD[47:0]
Tmod
MCKE, MCS#, MRAS#, MCAS#, MWE#, DQM[1:0], MA[11:0]
Table 5.2.6 Memory Interface Timing
SYMBOL Tmck Tmch/Tmck Tmds Tmdh Tmod
PARAMETER Memory Clock Cycle Time Memory Clock Duty Cycle Data-in Setup Time for MCK Data-in Hold Time for MCK Memory Output Delay to MCK
MIN 8.5 0.4 1 2 2
MAX 0.6
8.5
UNIT ns ns ns ns ns
Revision 0.95
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MYSON TECHNOLOGY
6. PACKAGE DIMENSION
120/128/132/144/160/184/208/256L OFP 28 X 28 X 3.32 mm 2.6mm FOOTPRINT D1 D2 D A2
0.05 S
MTL003
(Rev. 0.95)
A1
A
E1 E2 E
B
;L1
4X 4X e
1
aaa C A-B D bbb H A-B D
C
b e
ddd M C A-B S D S
C
2
SEATING PLANE
SYMBOL MILLIMETER INCH MIN. NOM. MAX. MIN. NOM. MAX. X 0.25 3.20 X X 3.32 4.10 X X 0.010 X X 0.161 X
R1 R2
ccc C
S
3
GAGE PLANE
0.25mm
A A1 A2 D D1 E E1 R2 R1 1 2 3 C
L
3.60 0.126 0.131 0.142 1.205 BSC 1.102 BSC 1.205 BSC 1.102 BSC X X 3.5 X 8 REF 8 REF 0.20 0.004 0.005 0.008 0.75 0.018 0.024 0.030 0.051 REF X 0.008 X X 0.010 X 7 X 0.003 7 X 0 0
30.60 BSC 28.00 BSC 30.60 BSC 28.00 BSC 0.08 0.08 0 0 X X 3.5 X 8 REF 8 REF 0.09 0.45 0.20 0.15 0.60 1.30 X
MIN. NOM. MAX. MIN. NOM. MAX. 0.13 0.16 0.23 0.005 0.006 0.009 0.40 BSC. 0.016 BSC. 25.20 0.992 25.20 0.992 TOLERANCES OF FORM AND POSITION 0.20 0.008 0.20 0.008 X 0.08 X X 0.003 X X 0.07 X X 0.003 X NOTES:
1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. 2. SIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. THE MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 mm. 3. THE TOP PACKAGE BOOY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BOOY SIZE.
0.25 0.003
L L1 S
Revision 0.95
- 64 -
2000/06/14

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